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In this free webinar, participants will learn all about thermal resistance network modelling, and how to find the resistance values with a detailed thermal model. All of it with online simulation in the cloud. A professional simulation project will also be provided to follow along during the webinar! Thermal resistance network models are therma
I am working on UMC 65 technology. My area of research is the reliability of circuits. In order to find out the degraded value of threshold voltage from a model equation, I need the value of the lateral electric field(E0) in UMC 65 nm technology. kindly suggest me.
Hi, I would like to bias an array of 128 current steering DAC's. I have made a current source as well. How would I bias 128 DAC's using this single current source? If I bias all 128 directly, would the added capacitance create startup issues?
Hello, I am working on a project for a course where I am required to design a differential OTA and implement the amplifier's feedback using switched capacitors. I would like to design the switched capacitor feedback network first, while i work out some kinks in my differential OTA, and thus would like to implement the feedback with an "idea
Apart from feasibility of battery operation, start with a clear specification. What's the intended operation volume over that you want to achieve "constant" field? Whole body? Only a small zone? The answer greatly affects the required magnet coil size and power demand. According to the low frequency, the problem can be described as purely
Hi All, I need to develop an circuit and antenna that will be placed on a person's body, and generate a constant electromagnetic field (for medical purposes). The definitions I received for this project is to generate a field from 10Hz to 700Hz, with field strength of 0.2 mTesla (that is 2 Gauss). I'm not an RF engineer and have very limit
Hi !, my name is Mariah and I am new in this forum. I have come and joined this forum with really high hope that I would get some help from you people. So I have been working for a project that I really want to finish. I want to built a circuit that automatically disconnect after a certain period of time. The time can be manually changed an set by
I'm work to use my STM32L475 IoT with bluetooth module ( SPBTLE-RF/spi/BlueNRG-MS) I need some help please I don't know the principe, someone give me an example (STM32_IOT+LED+Bluetooth+android) :)
Hello, I have Xbee Zigbee S2 2mW. I can enable security AES-128 key by configuring it through X-CTU. My question is can the key be set automatically over-the-air by sending commands from my laptop, so that I do not need to use X-CTU?? Moreover is there any chance when I have a mesh network of lets say 5 nodes, to automatically cooperate and chan
For Fast Arbiters for On-Chip network Switches , what is the difference between Proposed-I and Proposed-II topologies ? 156427 156428
Hello Friends, I have recently came across a text of impedance transformation provided by a tapped capacitor arrangement. Its a rare and unique text explaining the working of tapped capacitor network in terms of conservation of power. figure 6.31a) is an untapped case when no tapped capacitor is used..fig 6.31b) uses a tapped capacitor networ
Hi all, I have recently done layouts of some analog blocks such as op-amps, current source etc. Upon getting them reviewed by an experienced individual from the industry, I recieved the following comments: 1) Do not share source/drain terminals and instead use multipliers. 2) Do not share dummy transistor source/drain. Instead keep minimum
hi, how did engineers decided to use AC electricity of 50 Hz frequency for homes? why not any other value ? what if we change frequency to some other value say 75 Hz or 100 Hz ? will it have any side effect ? thanks
I'm using GPDK45 Layout is LVS clean Error logs : __________________________________________________________________________ *************************************************************** Reading schematic network Reading layout network inputting network test_1.ldb Preprocessing schematic network phase 1 (...)
Why do you rarely get low voltage all-SMD sync buck schematics with say three SMD power FETs in parallel? Surely, paralleling SMD FETs here is the way forward as it allows the solution to avoid using a FET heatsink, which would significantly up the cost.
Hi to all, In a my project I am using an Altera/Intel Cyclone IV FPGA. For some reason, the IO pins can be drivered with a negative voltage (-3.3V) that I would is interpreted as logic level 0. The problem is that the IO pins of FPGA not support negative voltage. I see in some circuit, that it used the BAT54 diode for protect the IO p
Questions: 1. What do you mean under "polarized" - applied voltage, or doping type? (I think, you mean the former). 2. What do you mean under "bulk" - body of SOI MOSFET, or substrate region under BOX? 3. is this FDSOI or PDSOI? (i.e., fully depleted or partially depleted?).
I am new here and don't know where else I might find an answer to this question-or which forum here would be best. This is a serious and important question so I hope it is not inappropriate here. As some of you may know, tens units or specialized devices are used by some for sexual stimulation. Some users will stim for hours at a time over the c
I need to switch some ressitors into a resistance network, but this means I have a resistive load on my source as well as drain of the fet. Can I do this?? see attachment
hello, i would require some advice on the capacitive DC-DC Converter that can generate several selectable DC voltage sources from a single given DC voltage source. The generated DC output voltages are multiple times of the input DC level when unloaded. It uses the concept of the Dickson charge pump, by multiple flipping of the charged capacitor ont