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Hello, Does anyone know what is rule of thumb for maximum current density on PCB tracks (Extracted from a DC Drop Analysis) ? I know for wires is usually 500A/cm2. How do I know if a local hotspot with 2000A/cm2 or 5000A/cm2 is bad or not. Thanks
Hello, i have a track and hold clock goes from 0-1V,C=15pf Vth=0.2V k=250 (no body effect),as shown bellow. What is the maximal clock frequency i can use to have 0.125*LSB accuracy at 14bit resolution? Thanks. 159558
Hello everyone I'm playing with some kind of 3 phase motor controller and i have issue with high side mosfet driver. My circuit seems to work well until HV voltage rail will be increased to some level. When it reaches about 150V the high side drivers are blowing up. I made a tests with no inductive load and everything was working correctly. T
I think you're looking for things like "body tie", "substrate tap", "well tap" and possibly die attach and backside grind (if you intend to contact the handle that way).
I heard in advanced nodes where the voltage is very low, if we share the VDD diffusion with two transistors , we can have an IR issue. But why is this ? Isnt the voltage same regardless of whether we share the diffusion or not ?
Hello i am using a 12v 7Ah battery to run a motor with a fan attached to it. Problem is the decrease in speed or say load handling capacity when I am increasing the wire length. I need to run a 7 mtr length of wire but in 5 mtrs only I am facing the problem . . .Normal LED lamps are working at that end but motor is not working . just I
I have a need to develop an optoelectronic system, and was not sure where to post. Looking for advice on how I can go about realizing a very specific kind of device: Eye tracker: with IR led, camera, USB output. Object distance is 2 cm or less, field of view 90 degrees or less. Sensor: CMOS, rolling shutter or frame readout. There are some other s
Hi All, I am having a confusion regarding the method used for selection of core size for high frequency converters. I know there is area Product Method and Core Geometry Method. I studied core Geometry method presented in both mentioned in Transformer and Inductor Design Handbook by Col. McLyman and Another Presented in Fundamentals of Power El
I am given a DEF, didnt create it myself. I was able to view the DEF in ICC2. I selected a specific layer (M1), and selected OPC and area fill shapes. But I dont see any of the FILL shapes. If II select "Fill cell", it highlights the entire cell, and not the shapes inside of it only. When I stream out this DEF as GDS using ICC2, I can see a f
I have gone through the OSI communication model and the associated levels. But I do not understand on how is this implemented in the Hardware level. Or let me put it like this. Suppose we have a USB (2.0 and 3.0) communication device from my Host PC to a Device connected. Like, from the hardware perspective, I can understand and try to design
Hello, I am a beginner in FPGA development. I would like to design applications in Financial Technology, Quantitative Risk Management/Simulation, High Frequency / Low Latency Algorithmic Trading, AI / Machine Learning and Digital Signal Processing. I am planning to buy the Nexys video Artix-7 to start developing the core FPGA design skills an
The airport area is considered a "golden place" for installing LED screens. Because of the vast space, the number of people can reach up to millions of people every year. Customers are extremely diverse, so this is an ideal area for advertising and product marketing. However, when embarking on the application of any technology product. Then busine
I usually have my layouts done by a third party, and they generally insist that no vias ever be placed underneath large capacitors and inductors (not referring to via in pad). See below: the pink shaded areas are via keepouts. I can understand this caution in a couple situations, like if it's an inductor with a conductive body (very rarely the c
I want to check if a DEF view matches Layout view (similar to LEf vs. Layout checking), but in order to that, I can think of loading DEF in ICC2, converting to LEF, and then comparing LEf vs. Layout. I have access to Lef vs. LAyout checker tool, but not Def Vs. Layout. I was able to load the def and read it in ICC2 tool. But how do I convert th
I'm building a push pull dc to dc converter and when I measure the voltage on secondary of the ferrite transformer it gives me 25.5 AC output which is correct for the amount of turns on the secondary. When I measure after the full wave rectifier , which consist of 2 mbr4045pt shotkky diodes I get a voltage reading of 16volts dc on a 160 watt load.
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I need to do reverse engineering on .BIN file which read from Fujitsu MB91F067 processor Can any body help me on that?
The accidental reverse polarity must have damaged devices before the fuse blew. This might include body diodes inside mosfets if they're used. Or electrolytic capacitors. Etc. There could be a controller somewhere detecting something isn't right, therefore the unit doesn't turn on. Does it flash a code, or beep a certain number of times?
hi every body i need to design siw using imedance characteristic
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