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56 Threads found on edaboard.com: Body Area
various antenna parameters get affected whenever the antenna is operated near the body. what are some possible methods and technique to maintain or improve the performance of the antenna when operated near body. one thing which i am already considering is the separation between antenna and body(> 2d2/lambda). can you refer any paper or book (...)
I am facing problem regarding irregular negative PFC voltage jumping -400V to -427V. Can any body help me to resolve this issue...
Accumulation, if it's used / implemented properly, can be a better cap area than inversion. But if you want to use a standard MOS, your bottom plate contact is not the S/D but the body tie (tap) which in many kits is left as almost an afterthought, placed as sparsely as the rules allow. If you made a "depletion MOS" (like, N+ active in Nwell) then
Start with IPC-7351 As to the QFN's the acronym QFN is generic you MUST always specify the pad pitch, body dimension etc. as there are devices with pin pitches 0.5mm 0.65mm 1.0mm etc.
Hi all can any body tell about hot research areas in RF and microwave which can be done regards dhruva
I am planning to start a inverter manufacturing/ assembling unit in my area . Any body know good inverter board and its spares (microcontrler based) is available in india. Or give any suggestions How to start a inverter company ?
I have designed 4 stage NGCC opamp and provide the body bias for all mos in my design ( + Vdd for body of PMOS , Vss for body of NMOS) but it is a coincidence that source and body remain at same voltage for all MOS except Driver PMOS of first differential pair in which I have shorted the body and source by (...)
If it is a PDSOI process then pick a JI of similar voltage range, dummy out the well-substrate params and replace with a plain capacitance of sensible area and t=~1um. Because these deeper body flows look like regular MOS pretty much, only the well is freed up. FDSOI, it gets messy. BSIM won't cut it, BSIMSOI is a bit buggy, and anybody in (...)
hello hello can any body help with masters project topics on wireless or LTE technology? thx
Dear all, I am a Ph.D student and quite new to OPNET. I am trying to work on the IEEE 802.15.6 standard and am interested in developing a simulation for wireless body area networks employing IR-UWB sensors. Any knowledge regarding its implementation in OPNET would be really useful. Thanks a lot!
HI, In CAN rtl we have blocks like can_fifo.v can_bsp.v can_registers.v . . . what are they? can any body explain me the architecture of CAN. and block level diagram for CAN to write a verilog code? how to start a verilog code for CAN?
Please specify what is a person present for example it must be a person moving at speeds more than .001m/s for 90% of the time ; 20 % of the body area at 37 deg C must be visible to the sensor 90 % of the tme
Hi, I am working on a low power transceiver for Wireless body area network protocol. How do I get the phase noise specs of my PLL from the protocol specs. The protocol specifies the transmitter specs like EIRP, transmit mask etc. and receiver specs like sensitivity , ACPR etc.
Hi, I am going to design a low power biomedical transceiver for wireless body area network. Most of the papers in this field use 130nm technology. But I have no idea how technology impacts low power radio performance. Can anyone help /cite references to choose the proper technology? I understand that low power radio needs high Q inductor and h
Hi everyone! I am reading a paper about a CMOS LNA design. But I am not sure where the parameters' values of a CMOS technology are from??? The process used in the paper is SMIC 0.18um RF CMOS processes. The values cited are: (1) Gate oxide capacitance per unit area, Cox=9mF/(m^2); (2) body effect parameter, r=3; (3) One measure of the departur
Can any body give me some examples of the break down voltage between drain and source in any CMOS process? Depends on the process used, and should be mentioned in the PDK doc.
Hi guys, I'm strugling through the IPC-7351 standard and there is one thing (well, many actually) that bugs me. The component courtyard is defined as: "Courtyard ? The smallest rectangular area that provides a minimum electrical and mechanical clearance (courtyard excess) around the combined component body and land pattern boundaries." OK, great
hi every body i was using pads 2005(MENTOR GRAPHICS) i designed a 4layer pcb in it the problem iwas drawn a coupper pour in some area but the coupper pour was not coming in that place you can see the picture which i was attached above.but the cupper pour is coming in 2and 3layers but it was not coming in 1 and 4 layers so please solve my problem
Hi, i new to arm assembly i wanted to compile assembly program but getting some errors . code and error is shown as follows ...please some body help me out.. area ARMex, CODE, READONLY ENTRY ; Name this block of code ARMex mystart LDR R7,=1223 LDR R2,=3984 ADD R3,R7,R2 stop NOP NOP
Has any body any experience in this area? i need 200mW out put power. Thanks