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Borrowing Latches

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9 Threads found on Borrowing Latches
I guess this link will help you understand better.
There are two main problems with latches a) time borrowing is advantageous but it has a ripple effect. the timing aspect is something which needs to be tweaked in the STA tools to handle latches. This is much tougher than it seems. b) Testing : the DFT scan insertion tools cannot handle latches automatically. THIS IS BY (...)
what is the time borrowing in latches?
Hi, i think that there are no "good" or "bad" designers... If you want to follow the basic asic flow, then FFs are your choice. However, if you want to try something more exotic ( asynchronous circuits, glitch filtering, borrowing etc. ) then try latches. In any case learn to use both... Asynchronous design is becoming more and
my dear designer, my 2 cents, For flip-flops, the STA(Static timing analysis) tool checks and assures for setup check hold check For latches, There is a concept called as "Time-borrowing" so the STA checks for Time-borrowing especially for latches and not for flip-flops. Better understanding of timing paths are (...)
Hi, I have few questions : 1. What are the methods to overcome setup and holdtime violations? 2. What is clock uncertainity and the difference between clock skew and clock uncertainity? 3. What is "time borrowing" concept in latches? Please answer in detail if sumbody knows above questions. Thanks
What is clock borrowing & How it is working?
Unlike FF Latch has no equivalent scan cell. So you cannot insert full scan during DFT if you se a latch. Timing analysis can be done but is difficult than only FF design, as usually synthesis tools do "Time borrowing" around latches. check this page if u dont know time borrowing
Time borrowing means one latch takes the (a portion of ) clock period from its adjuscent latches by inserting buffers in clock network in proper position. yes. if you are interesting in this you can read this book more detail. something about this : --------------------------------------------- Slack passing is possible wi