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20 Threads found on edaboard.com: Buck Comparator
Hi all, Can you tell me in the design of dc-dc converters (buck, boost), what type of comparator should be used? And how about the specification for the comparator? I designed the hystersis comparator for buck converter with the switching frequency is around 1 MHz, however, when I simulate it in the (...)
Many low-cost buck converters for applications not involving RF use hysteretic control. I'm sure their block diagrams (in some cases) would be enlightening. You may not (probably don't) want much deadband / hysteresis because that is going to make for more low frequency ripple voltage on the output. If you have a simple comparator you may end up a
Hello, I want to buid a (foolproof) battery charger using a (synchronous) boost topology but I've just realized that there's no protection at all (for the Mosfet switches or for the output capacitors) if the load is suddenly disconnected (accidentally or not). That's it, if the main inductor is "charged" (I'm talking about medium power converter
Hello, Consider a DC-DC buck in PWM mode. Let us assume that this converter goes to DCM mode. In this scenario also, we use compensator in the loop. But, in case of PFM mode, we do not use any compensator. What is the explanation for this? I'm not understanding this concept. Thanks, Rama
Hello all, I would like to vary the output voltage for my buck converter by a vary between 0 to 3.3V V_HV vary between 0 to 100V Can you help me how calculate the relation between V_DAC and V_HV :bang: How i calculate R1, R2, R3 :?: 117186 Thank you
Hi I tried modifying buck boost converter in MATLAB as flyback converter referring to the book Fundamentals of power electronics by Robert.W.Erickson. But it is not giving expected output as per the duty ratio. The output voltage depends only on transformer. Please help me with this. Thank You
The buck converter is able to be driven by hysteresis, built around a comparator. I have not tested this schematic with hardware but it's a start. Adjust values to suit your purposes. The sense resistor can be a sma
I am working on a hysteretic buck regulator. I know this topology is always stable. But I have a question about the open loop gain of this topology. Since the comparator is a non-linear circuit and I do not know how to use linear model to represent this block. I just got a feeling that the loop gain is not very high. Does anybody know how to
Hi,all I am working on a project of on-chip DC-DC buck converter. I know that the PWM block is used to transfer the error voltage(between Vout and Vref) to be the duty cycle.However I have no idea about how to choose the amplitude Vp of the sawtooth signal in PWM controller. Since the duty cycle d=(Verror/Vp). Can anyone figure out this pro
are there any specific tips or precautions to be taken when designing a buck converter with a 10 A output? for example, are there stages needed? or extra safety circuits needed anywhere? or can a basic configuration work just fine? ive constructed one and im using a UC3843 PWM controller for the gate drive of the mosfet and my inductor is a fer
The input signals to the comparator in a current-mode buck converter are not digital pulses. But it's correct to use a comparator in this place, and you should not compensate it rather than make it fast. The output of the comparator is in fact a "digital" on-off signal, what should be the purpose of compensating a (...)
Hi All, I am now designing a dc to ac buck converter . There is a comparator in a voltage loop. I am now getting a severe phase delay when I tried to sense the output voltage and do the subtraction with Vref. Is it possible that the delay is mainly contributed by the comparator? Thank you very much,
Your first opamp should have some frequency compensation components, Resistors and Capacitors to stabilize the loop. for example, a resistor from the output of buck regulator to the inverting node of the opamp and a capacitor from inverting node to the opamp output. This network forms a pole in the frequency domain. Your TP9 voltage
hi, i have a buck converter and the switch is controlled by a pulse source. I have designed it in hspice . What i want to do is to control the pulse source with variable pulse width but hspice doesn;t give me that option. Can anybody tell me how to change pulse width in time ,and having the Vpp constant?? thank you
i m interested to model buck converter by simulink. i want to use digital controller(ADC, compensator,DPWM/DAC); I WOULD BE THANKFUL IF SOMEONE PROVIDES MATERIAL REGARDING THAT; MAIN PROBLEM WITH ME TO MODEL DPWM/DAC to get duty cycle to drive the gate. thanks in advance.
hi, Im new on buck design. Just wonder, for current mode buck shown in the attached pic, how to decide the value of Rf? And if I use current comparator instead of the voltage comparator as the modulator, then I don't have to use Rf, is that correct? Then, which is better? current-comparator as the (...)
in the buck converter,when both PMOS and NMOS are shut down,there will be a ringing in the node LX,as in the enclosed picture what is this effect? and how to eliminate it?
Which type of comparator can use in the buck converter? the switch frequency is 500k~1MHz. Thanks.
I have a few question about buck Error amplifier compensation problem need someone help me. 1 Why the eror amplifier need compensation? It is just a comparator. 2 how many types compensation method tha I can use? 3 How to guarantee the close-loop stability and how to simulation in behavior? Thank you!
Dear All : Does anyone know how to desgin PFM modulator of buck regulator , I read some paper , The circuit is like Ve compare with VH , Vl , The Using R_S latch to generator the PFM mosulator . Is it correct ? How is depant on the loading ?? Thanks