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35 Threads found on edaboard.com: Buildgates
Hello, I'm an engineering student, we are using different software in the lab and I would like to know exactly which tool belongs to which package buildgates Extreme cadence is part of Cadence EDI? Cadence NcSim and NcLaunch are part of Cadence IUS?
HI i have a serious problem with power estimation in PKS.I read in "Low Power Option for Ambit buildgates and...." reference that to estimation of power in PKS i must have a tcf file,so with much trouble i could generate a VCD file using Modelsim-Altera and converted it to tcf file using pksvcd2tcf.exe from PKS.here are both of them.but when i tri
Cadence RC or buildgates script has synopsys-compatible mode. You can contine to write synosys scripts and run them in Cadence environment.
Hi, I installed IC5141 and it worked fine. setenv CDSDIR /tools/cds5 setenv CDS_ROOT /tools/cds5 setenv CDS_INST_DIR /tools/cds5 setenv CDS_INSTALL_DIR /tools/cds5/tools.lnx86/dfII setenv CDS_LIC_FILE 5280@localhost.localdomain setenv CDS_Netlisting_Mode Analog /tools/cds5/tools.lnx86/bin/lmgrd ?c license.dat I insta
Well I think for synthesis (from Cadence) you can use buildgates (bg_shell or pks_shell, you'll have the Ambit std_cells) or RTL Compiler (RC - I've never used this tool, I wish too ). And if you want, you can use DesignCompile (DC from Synopsys). You can synthesis with Xilinx too (you can download Xilinx WebPack from their site, it is mean
Dear all, In my design, total power consumption estimated after synthesis by Cadence-buildgates is: Internal Cell + Leakage + Net = 0.2904 + 3.9775 + 0.3833 = 4.6512 mW While, after place-and-route, Cadence-Encounter reports: Total leakage power = 337395.002511uW Can anyone tell me why there may be such a diffence? what might be w
Hi everyone! I need to do some synthesys of simple combinatorial cirucits using build gates. I've tried to read manuals and tutorial but it's a lot of stuff. Is there someone who would tell me how to sintetize a simple vhdl files and how to read the reports of area and delay? thanks and sorry for bad english.
hello all, i am using Cadence buildgates tool to synthesis rtl for cmos90nm STM technology. The logic is as big as half a million gates. My issue is the buildgates stops working after a few hours try with following error: INTERNAL_ERROR: (mem_enomem2_from) - no memory available for allocation. Exiting... Is there any solution for this er
Hi all, I had a problem when I used buildgates Synthesis tool. I import verilog file, timing library (.tlf) and do synthesize and optimize my design. But when I write to netlist it can't dissolve my design into std cells. In my netlist file, it also call many instance and map pin when I call in my top module. Ex: kenh8 A8(.th_clock(clk
Hi everybody, I use buildgates to synthesize, I run script and the tools run into the bottom windows but I want to write it to a file to read. Ex in Synopsys DC u can use: source ./scr/constraints.tcl > ./report/rpt.txt but in Cadence I can't do that. Pls help me. Thanks.
when people want to perform synthesis using buildgates,they need .alf file, lets say that we dont have that file and only have .db file (synopsys),so how to convert .db file to .alf file?
A tutorial on how to use Cadence Ambit Build Gates in synthesizing Circuits. This tutorial is from the University of the Philippines,Diliman Microelectronics and Microprocessors laboratory.
Dear all, I want to choose one synthesis tool between buildgates and Incentica's Design Craft (whose shell command is DC like). I am familiar with DC but buildgates. My understanding is that the timing path which is an object at the DC environment can be extracted attributes. Users may get the clock's arrival time for each timing pa
hi all, Im using artisan as my technology library for synthesis in buildgates. But I cant find any symbol file (.sym) in my artisan folder. Artisan has .edif file in it. Is this edif file represent the symbol. If yes how can i convert it to .sym file and where can in change the file. Siva
hi guys, After synthesis using buildgates, i have import the verilog design to icfb. But once in icfb, there is error shows: verilog defination for module DFFTRX1 was not found. Using lib silterra18 cell 'DFFTRX1' view 'symbol' as its symbol. I have already created the symbol library for this library. Can anyone hel me on this. thanx
I have a problem in optimizing my design using artisan library in buildgates synthesis. Once i optimize the design it shows a : WARNING "Cannot find symbol library 'typical.sym' " Hope I can get help on this.
hi, When you synthesis your design using cadance buildgates, generates a timming report. In the report, could some please explain me the meaning of some terms like . Other End Arrival Time 0.00 - External Delay 1.50 + Phase Shift 10.00 = Required Time 8.50 - Arrival Time 1.31 = Slack Time 7.19 This is the timming report i got . I
hi, When you synthesis your design using cadance buildgates, generates a timming report. In the report, could some please explain me the meaning of some terms like . Other End Arrival Time 0.00 - External Delay 1.50 + Phase Shift 10.00 = Required Time 8.50 - Arrival Time 1.31 = Slack Time 7.19 This is the timming report i got . I
hi, When you synthesis your design using cadance buildgates, generates a timming report. In the report, could some please explain me the meaning of some terms like . I have an idea , but i am not really clear about this. Other End Arrival Time 0.00 - External Delay 1.50 + Phase Shift 10.00 = Required Tim
hi Do anyone know what are the things to be taken care while taking the netlist file from Cadence buildgates to first encounter. my problem is whenever i import the netlist file to encounter, it is giving only i/o pins and my core boundary and i/o boundary are not showing. can anyone give some suggestions and help me. thank