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142 Threads found on edaboard.com: Bulk Voltage
Hello, VBB can very useful for tuning transistors in low power applications. With VBB, you are effectively you are tuning the threshold voltage of the transistor by applying voltage to the bulk. If you want low leakage (e.g. at low frequencies or in devices where leakage is a problem) then you need to use VBB to increase the threshold (...)
Depending on how good (flat w/ temp, supply voltage insensitive, accurate in production) you want the reference to be, you have a few choices. Simple resistor, delta-VT, or bandgap. The latter being a well trod path and doable in any bulk CMOS using the substrate-well-P+ PNP as a reference diode. Ton of papers out there. Most of them oriented at v
No , as I know this is not a fabrication rule and the designer can can connect bulk (e.g Nwell of Pmos) to another node, but in most cases you must connect bulk to voltage extremes
Hi. My question is: Why High value of signal OUT drop down when signal for read information is logical "1". The signal OUT drop for about 0.7 V. That is case when is treshold voltage lower (bulk and sours is connected together -mosfet with line of information and write line)-that we need to get higher value of OUT (logical 1). When I us
Hi, I assume high voltage spikes cause the fail. (Caused by wiring and stray inductance) Therefore we need to see your PCB layout. GND plane. Urgent for high speed high current switching. And there is no capacitor at 12V line. You need at least one low ESR bulk capacitor and I recommend an additional fast capacitor at each MOSFET_source. What s
The switch can not be really turned off due to the drain-bulk and source bulk current. The psub and drain or psub and source form the diodes, and pusb voltage is ground. When switch is off( gate voltage is 0), the two diodes are reversely biased, but there is still some tiny current going through the reversely biased (...)
And the real output impedance it's hoe. Where hoe= Vce /ic No. The real output impedance at low frequencies is set by the Early voltage Va, see At radio frequencies, other parameters like collector bulk resistance and transit frequency in combination with the reactant transistor impedan
You can use bulk modulation applying voltage between source and bulk and trying to control it There are many papers about bulk modulation and designing low power opamp using these techniques.
The bigger the MOS area the smaller Vth variations are. The bigger the area the bulk doping is less uncertain.
Hi, Your circuit will work. For sure you need to know the voltage drop in the diodes. As said before: Capacitors are essential. Many IC manufacturers recommend a unique capacitor at each VCC pin of each IC. Additionally a bulk capacitor will be useful. There are special IC s for power supply applications, they switch over automatically, while avo
If it is capable of 300Apk, the forward voltage drop can be predicted by piecewise linear approximation above saturation. A Silicon diode is usually saturated at 0.7V at Tj=25'C and any voltage rise above this comes from IR drop in the bulk resistance (ESR) related to it's size and thermal capacity. In fact ESR ~ 1/Pmax for the typical (...)
The 3.3V mosfet isn't appropriate for its 5V input voltage. Seems there is a voltage breakdown of the bulk-drain junction. You will need a 5V mosfet in this application. Or perhaps you can limit the bulk-drain voltage to max. 3.3V by design provisions.
What is the maximum duty cycle of your buck converter? What are the IR losses in the mosfet and inductor? These two questions give you the minimum voltage that must be maintained at the buck input for the thing to remain in regulation. What is peak DC bus voltage at lowest possible mains and full load? The difference between this and the value fo
generally PMOSFET bulk(substrate) terminal is connected to more positive voltage in the circuit but can we connect PMOSFET bulk(substrate) terminal to ground what happens if bulk terminal is connected to ground
DIBL is related to longitudinal electric fields, while body effect to source-bulk voltage. It's two different physical phenomena.
(H)NWELL_StampErrorMult, ErrorConnect usually means you have several (more than one) (H)NWELLs on same voltage level, but (each or any one!) not connected by an n+ bulk contact via metal to the same voltage (e.g. VDD). Separate (H)NWELLs with PMOS transistor source not at VDD level also must have an n+ bulk con
in tsmc 0.35, I have designed an op amp with dual supplies of +/-2.5V with bulk/substrates connected to vss(-2.5V). Meanwhile, I designed a comparator which uses a single supply of +5V/0V with bulk connected to GND. When I connected the output of the opamp to the comparator's input, the output of the comparator is pretty bad. Is it because the bu
Hi, I use tsmc18 RF model to model my NMOS. The RF model of the NMOS itself is a sub-circuit. When I run pss with spectreRF, it showed warning for the NMOS: "M0: Missing bulk-source diode would be forward biased", but I actually tied bulk and source together and they are tied to ground. I run transient and probe the voltage of (...)
Consider the charging series resistance* capacitance time constant is multiplied by the duty cycle of the diodes. If forward biased 50% of time, the ESR of diodes and supply is x2 . Diodes have a fairly low but non zero effective series resistance ESR that depends on bulk size of diode and thus voltage rise above saturation and thus current limit.
Hi, Imagine to have an NMOS. The bulk is p-doped and S/D are n+ doped. In the bulk, the majority carriers are holes, that do not produce any current for a given Vds. On the other hand, in order to have a current. Vgs has to reach the so called threshold voltage. In this condition a depletion region is created, and at the same time under the (...)