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218 Threads found on edaboard.com: Bus Controller
Hi All, I'm looking for a USB Hub controller (High/Full speed, v2.0, 2+ ports) that supports configuration by acting as a SLAVE on either a I?C or SPI bus. There are lot of hubs out there that do have I?C or SPI port, but it is configured as a MASTER for accessing memory peripherals like EEPROMs. Does anyone know of such a IC that supports co
Hello guys, System controller is between CPU and system memory, IOs etc.?? As i think on SOC there is CPU connected to bus and all peripherals IPs are also connected to bus?? So where is system controller on SOCs?? Its playing some role of management of data movement where as CPU plays the role of data processing ?? (...)
General guidelines: First think to check on what Logic it is working.. second is to check the comparability between controller and encoder whether we can interface the bus directly or not.. If above two are ok then you can GPIOs as a interface if there is no dedicated interface for encoder..
If you have the command order and a timing diagram for the bus, it should be fairly straight forward. You just write some controller for the chip and away you go. If you dont know where to start, I suggest a book on digital logic design and a VHDL tutorial.
Hi I was reading about PMbus protocol and I found out that each manufacturer has it's own GUI and USB to I2C/SMbus/PMbus adapter. I was wondering sinse PMbus (Power Management bus) is kind of becoming an industry standard in Power Management, is there a general USB to (...)
You can change the PIC18F2550 operation from bus powered to self powered.
what happens 1553 bus controller fails and what is the soultion
Hi I'm trying to get a Simulink model for Bidirectional DC-DC converter to be used for battery charge and dis-charge through a dc bus, the control strategy used is a two-controller control; one is for generating the reference current and the other one is for control the voltage, so the battery is controlled to charge when there is sufficient dc bu
In regards to a CAN controller hardware implementation much of the arbitration and error handling is done at the hardware level. These advantages in hardware implementation of the CAN controller allow many microcontrollers with limited resources to effectively implement a CANbus. Microcontrollers (...)
SSP (Synchronous Serial Port) is the module. SPI is the protocol. A Synchronous Serial Port (SSP) is a controller that supports the Serial Peripheral Interface (SPI), 4-wire Synchronous Serial Interface (SSI), and Microwire serial buses. A SSP uses a master-slave paradigm to communicate across its connected bus. en.wikipe
The CAN bus utilizes a Message ID centric system, in contrast to Ethernet which is a Node ID centric system, this approach allows a node to receive virtually all traffic on the bus. The messages received by a CAN node can be limited by the use of an Acceptance Filter, which determines the messages accepted by its
The CAN transceiver is required to tolerate high voltage at the CANH and CANL bus terminals. HV BJT or CMOS processes are needed to implement this feature, it's not possible with usual 3.3 or 5V high density processes.
You essentially you have two options: 1. Utilize an 8051 variant which offers a built-in hardware CAN bus module, like the Silabs C8051F5xx Series. 2. Utilize an external SPI/I2C CAN bus controller, like the
Can a memory controller support ECC if the SDRAM used has a width of x16? - - - Updated - - - And is it possible to use 5 of the x16 chips to create a 72 bit width data bus, and still use ECC? Thanks a lot!
plz tell me which controller family is the best, i need to work on microcontroller which is perfect one from all respects I like comparing to automotive because most engineers can easily relate to this. You are asking for the equivalent of a Lamborghini in speed, a school bus for passengers, a huge truck for lo
Hi, Im working on a board which has processors MPC8640/8641D from Motorola interfacing with FPGA through its local bus (LBC). To run the verification, I need BFM of MPC's local bus controller. Can anyone please tell me where can I find BFM of MPC's LBC?
Which pin on the ISA 8/16-bit bus has the Intel 8237 DMA controller signal "end of process - EOP" connected to it?
The FPGA wont have a DAC or ADC in it, but the board probably has one connected to the FPGA. And yes, you would need to connect that 8 bit bus to the DAC (and maybe some other controller signals too, like I2C). If there isnt one on the board, then yes, you need and external one. And I dont know what code you found on google. It will either be a DA
Hi, I'm looking for a processor with those feature: - price < $30 - DDR / DDR2 memory controller (64bits prefered), - a DMA engine able to transferts from an external parallel bus (running at 125MHz / 32bits) to the the DDR memory. Do you have any reference in mind ? Thanks, Franck.
NIC for which processor/data bus and which network type?