Search Engine

Bus Controller

Add Question

218 Threads found on Bus Controller
Its easy to interface DS12887, simple map it to port 0 as external memory .. here is the pin connections... controller<=>DS12887 P0<=>AD ALE<=>AS RD<=>DS WR<=>R/W You can connect CS to permanent ground, and, as your microcontroller uses INTEL bus timing, don't forget to connect MOT pin to ground .. see picture below .. Also, it
XAPP333 - CoolRunner XPLA3 I2C bus controller Implementation This document details the VHDL implementation of an I2C controller in a Xilinx CoolRunner XPLA3 256 macrocell CPLD. CoolRunner CPLDs are the lowest power CPLDs available, making this the perfect target device for an I2C controller. Design Files: coolvhdlq.htm (...)
Say Data from internal bus is 32-bit width, Data can output when output clock is high and Data when clock is low.
Could any one please explain the differences between.... 1) I2C bus core 2) I2C bus controller core 3) I2C master core 4) I2C slave core Thanks, Sujith Chakra
anyone know about CAN bus system?
What type of LAN? What type of interface bus? For common 10/100 Ethernet and a generic parallel interface bus, I've had good luck using Micrel's MAC+PHY devices: If you search Google for other Ethernet controllers, good keywords are "MAC" and "PHY".
thanks both of you. My concern is : When MasterA read SDRAM, before sdram return data, there will be a cas latency at least, if next time masterB read SDRAM, there will also a cas latency at least. But if we use proprietary bus,we can hidden the second cas latency. Actually, I don't have a clear architecture of this kind of function block, Ca
I need to port a PowerPC 405GPr design from a daugther card to an embedded system on the main board. The External bus controller will drive three FPGAs. These FPGAs will be scattered across a fairly large board. Looking at the reference design from AMCC, they do not seem to buffer the address or data lines at all. They just seem to daisy chain
Is there any reason to go with RS232. U can use CAN for better communication and u can have many controller on single bus. but if you want to go with RS232, u have to design ur own protocol like vikramprataapsingh suggested.
as i remembered, the memory map boundary is 4k, with 12 bits. it saves the logic overhead in AHB bus controller, who only have to decode first 20 bits in address bus to select a slave.
@ltera's NIOS devkit uses simple bidirecitonal PIO module connected to Avalon bus and SW driver for character LCD as memory mapped peripheral. If you want pure HW controller, you need probably some sort of state machine based on commands from LCD's datasheet. Regards Paul.
burst size and width of the data bus are not related to each other. burst type, size are setting up during DRAM init. It is your desision as designer what is desired width (ie, how many DRAM chips you) need regards,
I have ENC28J60-H ETHERNET controller DEVELOPMENT BOARD from Das anyone have working examples ohnly TCP protocol for SPI-bus ENC28J60 for PIC18 controllers? How many sockets can I open? Thanks.
Be careful: the printers DB-25 connector is a proprietary HP bus, not a common parallel port! Read more about it here: or here: The original cable pod is shown here:
Hi There are nice app note on OSRAM site show how to connect OLED dispaly to micro controller to 8080 system You will need to emulate a 8080 bus on Dspic - easy just use I/O port I f you are writing in C language i can send you some code All the Best Bobi
Hi, I'm searching for a Graphics controller with embedded ram in non-bga footprint (f.e. tqfp) like S1D13806 (this device is not more manufacture) I'd like tft - crt - tv output with host interface for an ARM microprocessor. (16-bits or 32 bits host bus) any suggestion? thank you in advanced best regards
I have a Spartan 3E starter kit with Micron MT46V32M16 DDR memory and I tried to use the Xilinx multi port memory controller (mpmc2) ip. I need to write the DDR from my vhdl code and I need to read the DDR from Microblaze with OPB bus. I downloaded all the exemple in the Xilinx site but I don't find this configuration (mpmc2 with OPB and NPI); ma
There is a Free IP from Xilinx called OPB_EMC (external memory controller), it can be used for SRAM, FLASH and memory mapped periphals. But the processor have to support OPB bus. If you are using microblaze or PowerPC, both support OPB bus, if you are using another processor, ypu can search in , there you can find SRAM control
Hello, I have a Xilinx Spartan 3E starter kit and I use the EDK 8.1 Microblaze with the DDR dram controller in the OPB bus. I write and read well a single access 32 bit; I need to know in which mode I can use the burst mode when I write in the DDR (I need to increase the bandwith in write mode). May sameone help me please? Thanks Daniele
get hold of this book The SCSI bus and IDE Interface Protocols, applications and programming