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24 Threads found on edaboard.com: Cadenc
Thanks. If I have the eye diagram, is there any code that I can automatically measure the eye height? I mean in cadence environment.
In case you just need to simulate/extract it in cadence with Sonnet tool EM simulations for the inductor, you can directly read the L values following the S-Param simulation. This is a good tutorial... For transformer parameter extraction, you can check this one as well....
Hello HAIDE, No, cadence Orcad is not the same with cadence IC design. OrCAD is a low-frequency simple circuit simulator with PSPICE. cadence IC design is focused on ICs, more complex stuff, semiconductor integration and mainly, circuits implemented in semiconductors ( Si, Ge, SiGE ) depends on what you use. From what I know all (...)
Hi, I have designed a folded cascode using cadence virtuoso. I want to do simulation on this using Spectre to calculate the differential gain, freq response, CMRR, PSRR, pole zero analysis. I am new to cadence and do not have much idea about the various types of analysis avaulable in spectre and how to use them. Somebody please help me out!
what the purpose of "Verilog-XL" tool from cadence? the options available in Verilog-XL's are: 1. Incisive verification environment 2. Incisive P2C Methodology 3. Incisive Design Team simulator 4. Affirma simulation analysis environment is it the option only for file and its compiling, elaborating and simulation or can we do the .vhd
Hi, I am designing wide band lna and freq range is 0.7~2.7GHz am using noise cancelling technique, but gain is not flat. and linearity is poor in 0.7GHz than 2.7GHz. Is there possible to use shunt peaking inductor to get flat gain and how to improve linearity (I'm using cadenc for simulation)
Hi, I am designing wide band lna and freq range is 0.7~2.7GHz am using noise cancelling technique, but gain is not flat. and linearity is poor in 0.7GHz than 2.7GHz. Is there possible to use shunt peaking inductor to get flat gain and how to improve linearity (I'm using cadenc for simulation)
To misure the output caracteristic of a LNA in cadence we can use Spectre and sp analysis, hence choose sp anlysis, then you have to choose the input and output port of LNA ande the frequency range for the correct analysis and then you can run the simulation. After the simulation you can gon in direct plot-sp analysis ad choos your favourite parame
Hello everyone, In cadence, when run LVS checking, we get the warning: psub_StampErrorFloat and psub_term_StampErrorFloat. What is reason and solution, please help if you know. Thanks.
Hi, I am running mixed signal simulation in spectre-verilog simulator with digital blocks implemented using verilog and analog blocks with transistors in spectre. I have created a 'config' view to simulate it. When I try to click 'netlist and run' button, the analog and digital netlist are getting generated successfully, but after the creati
Hello, The problem is as follows, When I put 10ps for the maxstep in the option of transient simulation, I saw some steps running at 6 or 7 ps. When I set both step and maxstep to 5ps, then the simulator run at 2 ps for some step. Finally I tried with 1ps, then 50as appears.... How could define a step that I want just like in Hspice or ADS
using the pwlf component from analogLib , u can find description and sample here
Hi all. can anyone give me a technology file for 0.5um or 0.6um for the cadence tool. we have the cadence tool in our college ,but i am not able to find out the tech file If any one on have it or u knows how to include it for cadence .. pls reply as early as possible..
check this link it is cadence tutorial khouly
Hi, Yes, you can find documents on the cadence website for running PSS, PAC, Pnoise, etc for LNA, Mixer, PA, VCO, pretty much everything. Just go to their website and do a little searching, it's under the spectreRF section. -Sam Here they are for your convinience Warning. Attachements deleted. Post links when are available. ht
Hi, I'm using PKS from cadence as synthesis tool. In the generated netlist, there are some "assign" statements. I know how to get rid of them in synopsys' design compiler or cadenc's rtl compiler. But I don't kknow how can I get rid of "assign" statements in PKS? Any idea how can I fix this? Thanks
When I start running cadence in linux FC4, it shows the following error message in the console: Loading "/cadence/IC5033/tools.lnx86/lib/libgdmtdm_sh.so" has failed. Error (dlopen): /cadence/IC5033/tools/lib/libvirtuos_sh.so: cannot restore segment prot after reloc: Permission denied Error (gdmiLoadDMLibrary): Could not load library (...)
Not exatly. By the multiplier you change the emitter area. But the total device size doesnot mean emitter area only. WHy don't u do one thing; you go for laying out the thing and measure it there by the ruler (for cadence excel, "k").... sankudey
Hello everybody, I installed cadence SPB15.5 in my Debian Sid but have a fatal problem when I use Allegro Design Entry HDL. I cannot add any component cell from what i selected but i can add any component cell from standard lib.Why ? This is the snapshot of this problem
I'm so confused that those Red Hat Linux OS products, My question as follows, Objective : I want to run cadenc IC5.0 on Red Hat Linux OS. Question: which OS should I choose to install? from this web site as below, I saw two kind of Linux solutions they offer. Sever Solution Client Solution I al