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DefValue of cdf parameters are updated from "parameter statement" in Verilog-A everytime I save Verilog-A code in cadence IC6. However this operation is troublesome. DefValue of cdf parameters were not affected at all in cadence IC5. Is there any method to disable this operation in cadence IC6 ? (...)
I have a question in cadence, say for example that i created a component (op amps ) and i intend to use that component in another schematic, for instance : i'll place it 10 times, however i want to change a value of some parameters in that op amp for 1 op amp without affecting the other 9, is there another way to do so other than creating a separ
Hi all, I'm at the point in my design where I want to start simulating with parasitic capacitance extraction, but I've found that I've been unable to get any extracted views to simulate properly. The schematic view simulated fine, the layout passes DRC and LVS fine, and the extracted view itself looks good, but when I switch the simulation view fro
Hi all, Yeah I know that cdf is something using which we can change the most basic parameters of the components. But, one question always linger my mind. When I say refresh (Ctrl+r ) in the cadence/icfb window, it pops up a window where it asks "refresh cdf's? ". below this question there will be many cells from the analog lib and other (...)
Hi dick_freebird, Thanks for reply. I can edit cdf once I created cellview. But I am not able to create cell view. when I am trying to create cellview it shows syntax error in verilog code. Can u plz helpme ??? Yes, the cadence-spawned veriloga editor will automatically check syntax and you may have to save-as
what's the difference between the job of cdf parameter, which can be set manually in cadence build-in dialog window when try to "i" an part on the schematics, and that of simulation model file, like .scs, which is loaded in the procedure when try to do spectre simulation? Maybe some parameters are overloaded or dependence between parameters of t
Hi, I have placed an npn transistor from analogLib(that probably comes with cadence). when i tried to Edit->Properties->Object.. for the transistor, i could not find any collector-emitter voltage field in cdf parameter. However when i opened cdf Editor i found the Vce field is there. Can anyone tell me why cant i find it in object (...)
hai friends, may i know how to calculate Ion/Ioff for FINFET in cadence and theoretically. If any one knows please reply to this post thanks in advance
for layout ,all the cells are from ARTISAN std cell lib . for schematic ,all the cells are from vrilogin using cadence when i run lvs by calibre it show errors as follows: Ensure that this cdf has same terminal name as specified in this cell view. Nets will be printed in default terminal order for this component "Netlister :
Hi everybody I'm wonder does any one knows that if its possible to get the cdf (cumulative Density Function) diagram in cadence spectre? or it should be done through Matlab Appreciate for help and hints regards Farid
in cadence i hav simulated the circuit and tried to plot node transient response,but it doesn't showing the plot, a warning (no "VT" data for node "/netxxx" ) is displayed in the icfb window can anyone help me how to eliminate the warning " no VT data for node xxx in cadence".
Hi All, Ive got 3 questions regarding layout of current mirror and differential amplifier:- Q-1. Ive got a current mirror with the pairs having large widths such that their finger numbers are 100 and 200 ( so as to keep the finger width <10 um )... now for this if i go for common centroid it will take lots of time for routing... so my questio
I think you are trying to pass a swept variable in ADE L with name "w" that is the naming of transistor's width at the cdf so they conflict and that's why you get this error.Avoid using names for your variables that already are part of the cdf. HI jimito13, thank you for your reply but I didn't have any variable w.
Is there any DRC rule which measures width to check if it is even number? please let me know, thank you
Hi guys, I have .SCS files. And I do not know how to import them into cadence virtuoso. Is there anyone who has the experience? I want more details about it. Thanks a lot!
Hello! Do you know if i can change the temperature coefficient of a resistor in my simulation and how? I am using cadence. Thank you very much
I assume you've created your file under the cadence environment. Is that correct? In that case, in the library manager you should 2 view in the cell you created. One is the veriloga view, the other the symbol you first created. You can edit directly this symbol view to match your new veriloga. You might also need to check the cdf database. Sometim
Hi, I would like to create a buffer chain by having the # of fan-outs as a parameter. This is probably a cdf thing. i know I can instantiate multiples of a block in parallel with something like I1<4:0> for a fanout of 4, but I cannot parameterize this fanout with something like I1, for example. Any help would be great. Thanks in adva
Hi I have .cir file and I want to create part in cadence virtuoso with that model. Is it possible?
Hi, I created hierarchy in Virtuoso 6.1.x I created the transistors from scratch , I mean my basic cell is just a transistor with pins because I want to simulate my basic transistor with some more adjustments to leakage currents and some reliability issues , and than I built my architecture with this basic cells . My problem is I want to ha
Hi, While annotating the transistor for its operating point, i can display only 3 types of component display properties (eg, Id, Vgs, Vds or any other 3 types)... but if i want to display more than 3, say 4 or 5 such type of properties .... is there any way? thanks
Hello, I want to test a model of an op amp in cadence written in Verilog-AMS. I have compiled the verilog-ams code successfully. I have also created the symbol. But I have found problem when I have tried to put the symbol in a schematic window and simulate a test bench circuit. I think there is a configuration : creating a config view etc.. Pleas
Hi, all Under the cadence schematic design environment, I get a device symbol from the PDK, then attach it to it's model file. In that case, the simulation result is strange and wrong. If I get the symbol from the analoglib, the simulation result will be all right. I don't know what happened here. Is it something wrong with the configurati
hi , i tried to export cdl from a schematic. but the cdl is not showing correct model names like nmos,pmos etc. It is showing N,P . where have i gone wrong..? do we need to do some device mapping??? If you use cadence, try to change cdf parameters of your devices. They defines CDL translation (and not just CDL)
I'm having two issues with the cadence/spectre analog enviroment. Perhaps someone more experienced than me can help me solve them? 1) In the schematic: Next to my transistor are three lines of red text. They go as follows: "n18rf" *Error* nf=6 The first line is the device model name and the third line is the number of fingers.
I am not sure is this the right place to ask. What are these? Why they are done ? are they necessary? The layout drawings has only two colors,how to fix them? You should read about this in the cadence documentation... cdf is the Component Description Form, the part of the database that is mostly used for Analog
I used to cdl extraction, I want to modify some paramneter and model name, Bu ti cannot. In the net, I can find some way to modify auCdl. But This is not work for me. In my case, I have only 4 view component in the one cell, cdl, lvs, symbol, verilog. "cdl" is the key to extract cdl netlist. But I don't know how to modify it. when I ope
there are many ways to extract netlist from schematic in the cadence. I used one among many way. it was cdl extraction method. extraction process is following figure. Question : in Initialize Environment, Simulator Name is "Other : cdl". When I want to modify some device or model name, what I have to modify to change device parameter?
Hi, I am using IC5.0.33 in Fedora Core 4. The cadence runs fine except for the following things: 1. When I open a schematic and try to check the properties of transistor or resistor or any other component then the parameters like the lengt, width, multiplier etc. do not show up. All the cdf parameters are absent.
Hi ,,, any one can help to solve this error ( following lines taken from CDS log file) : \o cdf: An error occurred when evaluating callback. \o Callback: model->display => C035a_mosDisplay('model) \o \o Message: *Error* eval: undefined function - C035a_mosDisplay Thanks
Maybe the V5 waveform type is not defined. it is a bug in old version cadence. You can copy the V5 from the analogLib to your own lib, then edit the cdf of V5, you can define the waveform type
Hi, Did anyone try to make the cdf parameters for a component using SKILL on cadence before? I want to write it for an MIM capacitor.. How can i attach it to the symbol after creation? In other words, how to point to that SKILL file containing parameters? Thanks in advance, Ahmad,
hi when i export cdl netlist ,i have got the problem the nmos and pmos i got the param of modelname ,l,w but the res i can not got these param . why ???? deos somebody can help me ??? thanks advance!!!
hi, at first, sorry about my poor English. I got a problem with cadence "export netlist" I have defined cdf parameters of Width, Length, Drain diffusion area, Source diffusion area in schematic. But only Width and Length can be seen in netlist. How to make every defined parameters be showed in netlist. thanks.
It is OK to use different names for different netlists. You can edit them in the CDL editor. Please refer to cadence documentation.
This is not a cadence option, it is a design kit option. U can find the equation from the process documents.
hello all, suppose that i have created a symbol for a circuit that includes 2 NMOS's.....let call them NMOS_1 and NMOS_2. now, i wish to use multiple instances of this symbol to build up a bigger circuit.....but i wish to be able to have different values for W of NMOS_1 & 2 for each of the instances. i am told that this
Do you use the cadence tools ? If the answer is yes, maybe you don't turn on the netlist mode in analog. Yibin.
For more details of cdf you can refer 'cdfuser' ie the Component Description Format User Guide in the cadence Documentation.
All; I am using ACE (Analog cadence Environment) as circuit design tools. Now I want to import a SPICE package file (*.sp) as a sub-circuit in ACE, combine with other cells in the schematic to run the simulation. Did anyone have experience on the procedure of how to setup the cdf file and other steps? Best. Eboy
How to create an instance using skill languahe in cadence, say NMOS. I have seen the syntax for creating instance dbCreateInst( d_cellView d_master t_name l_point t_orient ) To be specific what should I enter for d_master. Also how can we edit the parameters like width and length of nmos thanks d