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37 Threads found on edaboard.com: Cadence Low Power
Hi, Generally Efficiency = (Pout/Pin)*100, here i give the input power using port (-20dbm = its equal to 0.01mw power ). So i know the input power, and output power calculated using P= V*I formula. If in this method i calculated the efficiency become too low.. I would like to know, whether this method is (...)
Hi, Generally Efficiency = (Pout/Pin)*100, here i give the input power using port (-20dbm = its equal to 0.01mw power ). So i know the input power, and output power calculated using P= V*I formula. If in this method i calculated the efficiency become too low.. I would like to know, whether this method is (...)
Hi guys, I am not familiar with DFT of calculator in cadence spectre. The problem is in frequency domain i observe very low resolution and steps are 200Mhz ! how can i increase resolution ??? 132731 I have a 2.5 Ghz signal and i cannot observe it ! and neither other tones !!!
In general, you bias a P-device On by pulling the gate low (or by connecting its gate to ground). Bias it Off by pulling the gate high, as high as its supply voltage. To measure current consumption, install a low-ohm resistor inline with the power supply. Measure voltage across the resistor and this lets you calculate current draw. Since (...)
Hi all, I have recently started designing a rectifier circuit in tsmc 90nm CMOS technology for harvesting purposes. I am using the RF library (RF/MS low power) for cadence and I would like to know how I should choose the capacitors for my design among the availble models (eg: crtmom, crtmom-rf, mimcap, mimcap-3t, mimcap-um,...). (...)
sir, We need to implement ckts., using varying Vtp and Vtn, but available technology is is only 180n. How to do this?
Dear all, I am studying the cadence low power flow, and I would need your help with some issues. 1. I have written a Common power Format -CPF- file (version 1.1) with 14 power Domains. Each switchable PD is created as follows: create_power_domain (...)
In general, fault coverage is calculated as the ratio of faults detected by your test patterns vs. the total number of possible faults. You need fault simulation for this. Im not familiar with cadence tool, just give you some hints, try to research more.
Hi, I am comparing Plain synthesis Netlist vs low power synthesis Netlist( i have only used clock gating low power technique). I am using cadence Tools. i find that there are unmapped points in low power netlist ( Red coloured "U") which is of clock gating as shown in the (...)
Try get lowpower papers on the internet. Otherwise check cadence,Atrenta,Synopsys,Apache etc., there you will find more such papers. Access Si2.org, it will also have lowpower stuff. There is one book "LPMM" from Synopsys.
CPF is from cadence UPF is from Synopsys / Mentor.
Hi All, I'm trying to implement Muli-Supply Voltage technique to a design. Basically, in my design I've two analog blocks operating at two different voltages, and I've attached a level shifter b/w the two. I've specified voltage of primary power net as 1.5 V for the first block and 1.8 for the second.So, now when I extract power intent from
In cadence virtuoso 6.1.4, Mosfets are present in gpdk180 library. can anyone say me whether these mosfets conducts in subthreshold reigon ? i need a mosfet with low power consumption. in which library wil i get ?. what are te latest libraries which are advanced in technology .
Hi i am sorry, i know you can use UPF/CPF for this purpose. But i dont have hands-on in it. I strongly recommend you to go through synopsys low power design manual, it has lot of details on power gating. For ur second question almost all tools support UPF/CPF, like Synopsys DC, cadence RTL compiler etc.
i have designed a low power beta multiplier refernce (70nA) as shown. The opamp is a 5T diff check for stabilit i broke the -ve feedback loop and plugged iprobe from analoglib in cadence. stb analysis shows phase margin of 20 deg and gain margin of 14dB with C=2pf. I m not able to achive better phase margin even after shifting the mirror po
I designed an lna,the input-referred 1dB compression point is shown below 76307 With the increase of input power, the LNA gain increased. I think the input-referred 1dB compression point is very strange I feel normal as follows, 76308
Hi, I am working on a low power design. I am looking for a pmos transistor with 0.5V Vdd and Vth. I'll be giving the i/p to the body of the pmos such that the Vth of the transistor will reduce. Can someone suggest where i can find a suitable tech file to use for simulation in cadence? Thanks
actually i am working on designing an low power pulse generator using verilog-A can i use tanner for it?? or is it a must to use cadence virtuoso?? or is there any other verilog-a simulators!!!! plz do help me!!! -prasanth
Can any one give me, tanner hiPer Silicon download links???? or any tanner HiPer Silicon tutorials or manuals!!!! actually i am working on designing an low power pulse generator using verilog-A can i use tanner for it?? or is it a must to use cadence virtuoso?? or is there any other verilog-a simulators!!!! plz do help (...)
i am designing a nand, nor, etc logic circuits(mosfet) using cadence @ 32nm technology.what should be the appropriate capacitive load that i have to use corresponding to fan out of 1?..............please give some links to read about this