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320 Threads found on edaboard.com: Cadence Noise
Hi all ; I want to plot a caracteristic of input current noise for an amplifier ( Schematic) in VIRTUSO 6.1.5 (cadence). there is someone know how to make it please best regards ;
Dear All, I am designing a conventional relaxation oscillator. The moninal frequency is around 2.85 MHz. When I try to run the transient noise simulation and use calculator to obtain the eye diagram, I got some weird diagram and i am very much confused. Attached you can see some waveforms obtained using the function eye diagram. The se
Hi all, i want do signal integrity analysis in cadence SoC encounter, i unable to do it.. i dont know how to do and analyse how to do it. can any of you help me out. appreciate your reply.
gangs, I am running .noise analysis in cadence's spectre. Two methods display the simulation results: method 1. plot equivalent input noise. This can be done by: locate spectre simulator menu-->results-->direct plot-->equivalent input noise. A figure will pop out. Then go to calculator's RMS function. The final result is (...)
Hi, 1. I am using IC6.1.6-64b.500.1 and my simulator version is 10.1.1.296.isr18 64 bit 2. I am simulating a basic downconversion mixer as shown in attached figure. I want to know the correlation between noise at RF (red) and noise at IF (blue). I tried to follow the following article:
Hello everyone, How can I find minimum detectable photo-current value? (in cadence, Post Layout simulation of a 3T-APS image sensor) the more i try, the less i succeed :sad:. Thanks in advance.
I'm a novice in cadence. And I have designed a ring oscillator in virtuoso. Can you please help in doing the PSS, Pnoise analysis in cadence? Quick and detaled reply will be very helpful.
hello i want to design a simple delay circut using logic gates in cadence virtuso. i tried many circuts like cascading of inverters ,using xor gates but i dint get the correct output. help me out.
sir i am doing 8 Bit folding 8 interpolating ADC in cadence. plz tell me how to calculate INL,DNL factor using calculator option of cadence tool. is there any other way to calculate INL,DNL factor. How to calculate noise margin and SFDR ?
Hello all! I am trying to perform some simulations on a TIA circuit on cadence Virtuoso. In particular I am interested in plotting the BER vs input power graph, however I don't know any method to do so. For a particular input power I could measure the output swing it produces and divide it by the the output integrated noise. Then get the BER
hi i have designed a downconversion mixer, i hv measured conversion gain, noise figure, linearity but not able to measure bandwidth or freq range of mixer. i tried PSS + PSP but in this only IF freq i m able to sweep but did'nt get the option to sweep RF frequency. can any1 suggest me wat to do
Hi, everyone. Can you tell me how to simulate the input referred noise of chopper amplifier in cadence? use noise, pss or pnoise? which is more suitable in this case? thanks in advance, best regards, Mirro
Dear all, in the cadence environment output noise can be simulated, for bandgap simulations the integrated output noise over 500kHz is about 10uV@dc, input noise 0.5V. The specified source is the supply with 1V ac amplitude. Is there some relation to the offset voltage of the bandgap input stage? Is the output (...)
May be this forum thread can help you, especially A. Beckett's answer.
If cadence finds the oscillation frequency as 20.xx GHz, Pnoise will also compute Phase noise at this frequency by nature of spectre. Have you ever tought to change "Relative Harmonic" to 3 ??
How do we define the noise file name in cadence in the vpulse properties?
Dear all, anyones whos knows how to distribute a tran noise simulation jobs on different cpus? How to distribute the intial seed? thx.
I am using spectre to measure the noise performance of my schematic with spectre in cadence . I wonder how the software to calculate the noise factor with the input noise and output noise . The simulation results show that noise factor doesn't equal to output noise divided (...)
It is simply due to limitation of small signal noise analysis in frequency domain. We can never get reliable result of phase noise for small offset frequency. This is true for any vendor's simulator such as Agilent ADSsim, Agilent GoldenGate, cadence Spectre, Synopsys HSPICE, Mentor Eldo, etc. See the followings. www.designers-guide.o
Hi, AdvaRes. I'm using cadence IC615. Do you know how to get the 'Waveform user guide' for IC615 ?