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28 Threads found on Cadence Output Impedance
The impedance which you have found by applying Load-Pull technique is NOT the complex conjugate of the output impedance of actual circuit. Optimum impedance is generally pretty different than complex conjugate of the output impedance of the circuit.Wrong. Ho
hi guys I want to know how to measure output impedance of opamp in cadence. Regards Arunkumar
Hello guys, I am designing a differential common collector Colpitts VCO and as usual I am taking the output from the collector of the transistor. This output will go into a buffer stage so therefore I am trying to design a matching stage between the buffer and the VCO so I can extract a good output power from the oscillator which will (...)
Dear all, I am using cadence to simulate an opamp's input referred current noise. However, i have no idea how to build the test circuit for it; since I cannot use a current source as a input noise source in the noise analysis. If i do, the bias condition will be disturbed. can anyone help me? Thanks a lot!
I tried to measure the input impedance of differential input stage of mixer using s2p analysis in cadence Spectre RF, I got same Z11 in following cases 1) When the Port connected deferentially 2) Using AnalogLib ideal_balun 3) Using RFlib balun (with Balanced output impedance set to 25 Ohms), with balanced (...)
Hello All, Question is really in the title. I have a folded cascode single stage OTA. As there are cascodes on the output drivers I am concerned as to what the Rout of the OTA actually is. Does anyone have any suggestions as to the correct procedure to measure the output impedance of an OTA? As a suggestion, should I place a (...)
hi, i'm designing a rf-power-amplifier and i want to get the CP1 depending on the output impedance of my amplifier. so i did a pss hb sweep over my input power. when i do this simulation and vary my output impedance manually for every simulation i get correct results for my CP1. but when i put a variable for the load (...)
Can anyone show exactly how to plot VF/IF in order to find the impedance in cadence. Thank you
I am doing my project in cadence...Here I am using epot circuit epot there are 2 more sub circuits.One is high voltage amplifier and injection i have to set the output voltage of epot to 193mV and 350mV... But i am not able to increase it.I can increase it till 124mV .But not able to increase after 124mV.Can u please tell me how
Hi all, I was designing a current-cell for a current steering DAC, I used a differential switch topology with a single MOS current source, biased at 10uA. I have attached the schematic. When i tried estimating the output impedance, i got an impedance of 361 Mohm, which I think too high. The way i tested the output (...)
Hi, can anyone tell me how to simulate the output impedance of a circuit using cadence? Please help! Thanks!
Hello everyone, I am designing a cascode current steering DAC, and I wish to determine the output impedance of each current cell. I want to know some methods to determine the output impedance of the current cell, which is differential-PMOS current cell. I am using cadence Virtuoso and tech lib : UMC 180. (...)
Hi, I don't know how i can use port (in cadence) in differential LNA and also, what resistance should i use in output of differential buffer? ( i mean that 50 Ω or 25 Ω because of two branches)
I am trying to measure input/output/inter-stage impedance for a Class E Power Amplifier working at 433MHz (switch mode PA) in cadence. Should I use ZM in SP analysis or ZM in PSP analysis? Which one is correct? In the driver stage, there are two parallel LC tanks which are tuned at fundamental and the 3rd harmonic. The problem is that th
hi Help me how to design a RF POWER AMPLIFIER,Class E power amplifier for 2.4ghz(for Zigbee applications).the input signal is of MSK. The output power we need is 0dbm,VDD=3.3v,f=2.45Ghz. i am working in cadence 180nm there is a need of Drive Stage or not if it needs which classification we should use for output (...)
Ouput isn't conjugated matched to the output of the power amlifiers.Instead Load-Pull technique is used to find the optimum load impedance which is seen by the amplifier itself. In cadence Design Environment, you can simulate your circuit by changing real and imaginary part of your load impedance on the Smith Chart and at (...)
Hi all, I have designed a Cherry Hooper amplifier in cadence using Spectre-Bsim4 for simulation and i want to find-calculate the total load capacitance at the output node (Vout1 as shown in the image). Do you have any suggestions or good ideas on how to do that? Best regards, Bill [i
Hi, Can someone please tell me how do i create a short circuit at the output port of a two port network on cadence? Thanks! Kas
i designing a balun in cadence, for converting differential inputs to single input,for that i have to maintain 50 ohms single input impedance and balanced output impedance is 50ohms, how can i design the balun with these requrements, plz tell me if u have the solution its urgent. can i use the ideal balun which is (...)
I have attached a pdf file that explains the simulation setup in ADS.All you should do is to make a s-parameters simulation independent of RFPA.. I have put the transformation ration as 2 and you can easily observe that impedances are transformed by this ratio for each Sxx How do you do the SP analysis in cadence?