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1000 Threads found on edaboard.com: Cadence Parametric Analysis
I have a VCVS instance in my schematic design. I can't find VCVS in layout after generate from schematic because there is no VCVS PDK in Layout. How can solve this problem? Thanks. Attached is VCVS symbol in schematic.
Hi guys, I have a schematic of OTA amplifier: 157362 I want to know the W and L that were used to design this OTA. I don't have more information other than the ones provided in this picture. since all transistors are in saturation, I thought about using the saturation current equation to find (W/L) ratio. by assuming
Hey guys, Please see the sketch of my circuit here. 157367 I want to do loop-gain analysis (a.k.a. loop stability analysis) for the top loop. In simulation I simply put a voltage source (i.e. VLG) in part of the feedback and run the LG analysis (ie. AC loop gain). My questi
There are some designkits built to support cadence Interoperatibility (for example IHP) and indeed that requires an extra license feature. PDKs without interoperability don't need that license feature.
Hello everyone. Currently, Im designing a processing element. This design is synthesis in Xilinx ISE Design Suite 14.7 using Virtex 6 XC6VLX75T-2FF484. I have problem on the timing analysis. The is no setup time and hold time reported as shown below. 157310 There is no slack for setup time and hold time. Durin
> Do I tell Installscape where DFII installation is already and then install Incisive ? No, you can install anywhere you like. The installations are independent (-ish) of each other. > Does Incisive have to be installed before cadence DFII or can it be installed after the cadence installation ? No, you can install anywhere you like. > Any spec
I think it's for advanced/experienced PCB Designers.I suggest you to participate into PCB Designer Trainings which are organized by Companies such as Mentor,Altium.cadence.. You should concretely learn a PCB Designing Package first then take advanced courses.
If you have for example the gpdk from cadence installed, you can quite straight-forward simulate with monte-carlo variations. What's your experience with cadence? The noise analysis is straight-forward. The MonteCarlo needs a bit of hands-on. I guess you refer to input-referred offset and noise?
I want to implement the wrapper using p1500 standard and implement WIR, WBY, WBR registers. So my question is there any software like synopsis, vivado, cadence etc available which can create the wrappers or have options to modify any generated wrappers or do i need to write verilog for each register and boundary cells? Thanks.
I have played with XCircuit (good, but unique mouse / bindkey behaviors hurt my brain after 20 years of cadence has worn a few grooves in the old gray matter). Its forte is high quality schematic output (Postscript based) but of course this also comes down to quality of libraries. I like Xschem, it has decent graphics and is easy to work with a
It depend on the circuit. Linear diff.pair should be checked with AC noise or pnoise analysis, for switched diff.pair pnoise or transient noise should be used. Otherwise I don't understand what are you curious about, "how to run analysis" is a bit vague question. Share details please (circuit, application, which analysis available in (...)
The phase margin is 72 degree when the gain is 0dB. However, the phase margin is close to 0 before the frequency reaches the unity-gain bandwidth. Is the op-amp stable? Why? Thank you. 157193
I did simulate a microstrip line in a EM solver, and extracted the distributed circuit parameters in a matlab script. With these parameters, I can build a circuit in ADS to which has comparable S-parameters with the EM solver simulation. This gives my linear circuit parameters. Further, I introduced some dielectric materials onto the microstrip
Hi, I am designing a differential folded cascode with both P and N-mos input transistor stages due to my different input common modes. During my transient analysis while running across the corners i am getting some offset of 70mv at worst between the two outputs. How can i minimize this offset. Note: I am giving a 0.3mV offset at the input an
Understand things correctly. Use correct terminology. Now, I want to import this S2P file in cadence virtuoso.You can never import S2P file to cadence virtuoso, since cadence Virtuoso is design frame work. However cadence ViVA can open S2P file directly by result browser. From my knowled
I'm failing LEC on registers that are equal to A%B construct. Where B is not a power of 2. I've read in several forums and online articles that some synthesizers do not support non-power of 2 modulus. But I have yet to find that stated in a cadence or Synopsys document. Do these synthesizers support non-power of 2 modulus? A doc link it appreciate
Common circuit i have seen but never thought let us say two power sources 10v and 5v in series with 5 ohm resistor in between. The current is 1amp, the net power by 10v source is 10w delivered but for the second source it is 5watt absorbed. The 5v being source how it can absorb ? I understand the resistor will dissipate what about source ?
Hi everyone, I'm a IC desiner. I am using VMware Workstation to run CentOS and cadence in its environment. I have promoted my PC memory Ram to 12 GB and allocate 9.7 GB to CentOS by VMware. However, when I open the Terminal in CentOS and run the "$ free -m" code in it, the memory info in CentOS is about 3GB. How can I allocate maximum memory RA
PDK's are mostly crypted and released in Verilog format.( There might be exceptions..) therefore extracting a model parameter from PDK data is more than difficult.. But some cadence Spectre based PDK may give you fundamental model parameters when you request "print model parameters" option.
Hi Everyone, I have designed a NFC system in which I can have around 100 V on the input antenna. So I need to attenuate the antenna signals (in terms of mV) before feeding them back to the reader module as well as keeping the antenna's resonance circuit quality factor. Hence, I would like to know an attenuating buffer circuit for my applicat