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Hi, try something like that or just google "cadence mixer simulation tutorial" and you could fing a lot of tutorials
I tried to post this message earlier, but it did not seem to go through, so I will try again. I am currently going through a tutorial for Orcad Capture and it is asking that I use a SMDRES footprint for my resistors. I know that surface mount resistors come in various sizes such as 0603, 0805, and 1008. So my question is how would a person know wha
How to plot ft, fmax for a 90nm mos transistor in cadence. Please provide elaborate steps
Hi i am working in tsmc 180nm tech. I need to do corner analysis at "ff","ss... and so on. I followed the tutorial in this link and was able to run monte carlo analysis but then when i changed the section from "mc" to "ss" or anything i am getting any error saying statistical
Hi guys; I've recently simulated a SAR ADC in cadence & now I want to measure the INL & DNL of the ADC. Each conversion takes 3us. I have designed this ADC for 5 bits & therefore we are going to have 32 states in the output. I've attached my 5 bit output to a 5 bit ideal DAC so that I can compare the analog input slow ramp to the digital codes wh
Does anyone know where I can find a tutorial about how to use the STB (stability analysis) function in cadence? open loop gain close loop phase margin and how to measure the offset?,
hello I used cadence with VMware and suse linux, for start I type in Konsole: cd ic then icfb& now I want to attach new library that I download from this site: but I dont know how I can do it:-( please help me, I am newbie in linux and cadence
Hi I am designing a two stage OTA using cadence . Need to run monte carlo simulation for offset voltage. can somebody give me any user guide. Thanks.
Where can I get detailed learning tutorial/video for PDN Analysis -PCB level for cadence 16.6? I need it urgently for my project. Thanks regards, Kumar
guys please help how to write and simulate verilog code in cadence? thanks in advance
Hi, Going to use cadence SpectreRF to check DCDC buck converter AC characteristic (gain margin, phase margin, crossover frequency). Any reference? or tutorial to use SpectreRF for DCDC? I think I have to use PAC (periodic AC) analysis in spectreRF analysis setting but I have no idea how to create DCDC testbench and also set analysis parame
Hi, Does anyone have any documents on cadence commands for command line. I am looking for any pdf or ppt for the same. Thanks!!!
tutorial: Creating a NONDEFAULT Rule (NDR) A way to make special rules that pass D
I have designed a CMOS class E power amplifier in cadence virtuoso of frequency 1GHz output resistance of 50ohm and input voltage source of 3.3v I have seen a tutorial for a simple power amplifier in that they have given a input stage and output stage also some matching network along with it. For what we are using the input and output stage
i have tsmc 130nm pdk files (cdb) i wanna add this library to my cadence ic 5.1 how can i ? please tutorial me
Hello , Iam sarat , i want to implement Signal integrity to my design , Iam using cadence orcad 16.6 . Please can you suggest with some examples and steps of how it can be implemented ? what are the factors to be considered . Any kind of tutorial is required . Thanks & Regards , sarat
This is probably a really dumb question, but I've scoured every tutorial I could find and just couldn't find the answer to this. I am trying to export an RLGC lumped model of some stuff I made in HFSS, and then dump this file into the mtline instance in cadence Virtuoso. The simulator I'm using is spectre. It seems like everything I've tried
Hi, there. I want to create a verilog netlist for a schematic (cadence virtuoso, version 6.1.5). From a tutorial I found online, it seems that I can do this by Verilog-XL. The tutorial shows me that selecting Tools->Simulation->Verilog-XL can invoke the "setup environment" window, but I can't find the Verilog-XL option at all according to (...)
Hi..,I want to do envelop following analyses in cadence for switching amplifiers, as tutorial contains the example in which linear amplifier is used and the same is not working perfectly with switching amplifier so,I'd like to ask the question that Is there any separate procedure for the envelop analyses of switching amplifier?