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62 Threads found on Calibre Virtuoso
Hello all, I am currently working on layout in cadence virtuoso having calibre tool. In inverter while doing DRC,I am getting the following error which I am unable to solve since 1 month and I didn't found in google. 1. Offgrid error 2. Orthogonal corners are not allowed at die edge. 3. related to M1,M2,GC coverage. (GC coverage less than 0.2
From the looks of the warnings, it appears the calibre setup for schematic is not set properly. Assuming you are in virtuoso and using recent versions of it and calibre, what is set in the calibre View dialog for "Schematic Library"? You can get to the dialog through the virtuoso menu (...)
Hi i ran calibre DRC and then when i run LVS i am getting an error "Schematic export failed or was cancelled". I did hierarchial and Layout vs Netlist option. Under the input section of layout every setting was by default and also the netlist tab everything was set and i also checked the "Export from schematic viewer" option. And then ran LVS. Can
I was using cadence virtuoso for my entire career(last 10 years) and never worked in any mentor layout tool(except calibre verification) Now my new project is going to start in Mentor Pyxis, I am not at all familiar with this tool. I am feeling very difficult in doing layout and modifying layout with this tool, is there is any way by which I can
To accelerate design, I used following commands for multiple CPU processing command in Cadence Encounter APR tcl file: " setMultiCpuUsage -acquireLicense 8 -localCpu max" It seems working fine. For Cadence virtuoso calibre DRC/LVS, may I use similar tricks to make it run faster? It's pretty slow for a large design. Also, is there a way
Hello all, I have a strange problem running DRC check using calibre. When I start virtuoso, license "111" is succesfully checked out and everything works fine (Schematic, Layout, MMSIM). I implemented the calibre skill interface in the .cdsinit and the drop down menu in layout editor appears. When I start calibre from (...)
This might be an obvious question, but, is there a label or 'lbl' subtype on metal 6? - - - Updated - - - Oh, I just saw your attachment. The cross doesn't seem to be overlapping the metal. Try putting the label right on top of the metal, it might not be attached to any metal and calibre LVS is just dit
I prefer klayout because you can import the tech file from Cadence to get the same colors and shapes as virtuoso, but on Windows, Mac and Linux... for free. It because very convenient on Windows to double click on a GDS file and get the same view as in Cadence. It also import calibre DRC results ... easy to see on Windows.
Hi, I have two questions: 1. Why for some cells, IBM_PDK and calibre is not shows on virtuoso menubar? 2 Why I get "RROR: Specified primary cell XXX is not located within the input layout database" error message while doing DRC on some cells? Where is the "input layout database" and how can I add other cells to this database? Regards
Hi all, I import a GDSII file in IBM 7RF technology and while streaming in I specified the LayerMap file (cmrf7sf.layermap) but while I try to do calibre DRC it shows me the following error message: ibmPdkruncalibre("DRC") Starting DRC on top cell in window:3... Unable to find valid layer mapping table. Please enter mapping file path manually
Dear Folks, I am installing Caliber 2011 versions (ixl_cal_2011.4_35.27 for 64bit linux and x86_cal_2011.4_35.27 for 32bit linux) on Cadence IC615 with IBM-0.13um CMRF8SF design kit. In Cadence virtuoso IC layout menu, I can successfully pop up the Caliber interface with Runsets, but when push the DRC buttom, it seems that Cadence can
I am using calibre to run LVS, and for one of my cells I cannot find the *. to be compared with the layout. How is this file generated? Can someone help with the problem?
yes, by checking the option "Export from layout" calibre exports gds2 for you. alternatively you can export from virtuoso tool and the give the file path these it can also work.
Hi I have a problem with my calibre Interactive when I try to run DRC for my layout verification using virtuoso 6.1.3. It's show the error ' The following products could not be licensed sufficiently". Is it related to the calibre license because the technician who install my calibre said the license is find. Hope somebody (...)
Hi all, I am using calibre to do lvs check. I got a lot of same kind of errors like below ERROR: Cell VIA12_2cut_N$$178120748 is referenced but not defined. Actually, I am using Encounter and export the gds from Encounter, stream the gds into virtuoso, and use the gds streamed out from virtuoso for lvs check. After I imported the (...)
Hi All, I would like to ask whether sign off LVS by tools like Assura and calibre is really neccessary for Encounter based PnR. Because the layout and schematic are all from the layout generated by Encounter. I think ideally they should be same, not like the custom layout design where the schematic and layout are generated seperately by differe
Hello I am using the 45nm IBM-SOI toolkit provided by MOSIS for my custom design with Cadence virtuoso. Right now i am working on the layouts of my design. I am using the calibre tool-suite for DRC/LVS/extraction. For a simple inverter although my design is DRC clean when i try to run an LVS i find that the tool is not picking up the ports in
While running DRC in virtuoso for umc90nm ,it gives an error as line 320 of (DRC selected file),unable to open or access file type and that file is ./ I dont know why that error occurs the restricted foundry document or the staff from UMC will give you a hint. basically, calibre is looking for
yes, it is possible to generate the schematics , but this method is a dirty fix. calibre tool(from mentor) will have an utility call ver2lvs . it will convert verilog to lvs netlist or cdl. now you can readin / import this cdl into cadence virtuoso editor to get schematics. once serious drawback is your schematic will look really ugly. all t
Has anyone experienced the following problem? I have ubuntu OS, and mentor calibre (2008 version), cadence IC610. With calibre PEX, I am able to extract "spectre" netlist without any problem. However, if I use calibreview for post layout simulation in cadence design flow (Analog Design Environment), the extracted calibre (...)