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28 Threads found on Cap Array
Hi, I am working on LCDCO design. We can program oscillation frequency by programming switched capacitor array. We find different cap curve vs sweep code with CC and RCC netlist, shown as attached figure. I apply AC current and measure imaginary voltage to calculate capacitor. The measure state is shown as follows. I use (...)
If you say the stored energy is 39?J from a 100nF cap, what is the time duration and ESR&ESL of load? Let me make some assumptions to estimate these. The ESR is 1Ω per watt per device.(Tony's rule of thumb)You have a 50W array something like 6S4P using 2W per LED for 6x3.7V for 22Vnom. Thus 2Wx24 LEDs, 6S4P, ESR=6*?/4=0.75Ω .
What do you mean by "using arrays"? Do you mean drawing a cap array? In cadence layout, you can draw one unit cap first then select and copy them. Then before you paste them, press F3 and you will get a window where you can change the number of rows and columns that you want to paste.
Hi All (this is my 1st post ;-) ), Would very much appreciate if someone more experienced than I (which should be about everyone else here ) would check the circuit in attachment (in JPG. can't upload a gschem?? 8-O). My doubt concerns the bottom part (resistor+cap combo) where the relays connect to ground... I'm trying to save as much powe
Does this idea seem applicable or is there another way? I think it's ok. But as you need a big array anyway, you could spend 8 more unit caps in series to achieve 0.125C - e.g. around the 1C scaling cap part - so you can build your whole scaling cap inside the array.
How to calculate the thermal noise from the switch cap array of a SAR ADC? Thanks
Hi there, I am trying to find a commercial chip that is digital controlled binary weighted capacitor array. I can use it with a digital control circuitry, to tune the cap value as I need. Is there one kind of this capacitor array? I dont know its professional industry name, so it is hard to search on (...)
The implementation would have to be an array of series resistors, each with a shorting device in parallel with it. The logic would be the inverse of the capacitor bank. For the parallel cap bank, you would close the switches to "add" a capacitor to the total. For the resistors, you initially short out all the resistors (...)
It depends on your circuit structure and design specification. You could add this parasitic cap in your simulation to check if requirement is satisfied or not.
Now I face a problem when using the Vncap to consist of a 6*6 cap array. I already find that the cap should be placed on the RX and BP layer when setting the 3rd terminal of VNcap in the schematic to be substrate. And if I just test a single vncap in the LVS ,it can pass; however when I (...)
I made the digital control as a state machine and find that timing delay introduces spikes in my cap array output. some use counters and some shift register and combinational logic for the digital control, which is better,easier and more robust to implement.
I am working on 12-bit SAR ADC design, in which i make use of capacitor array to build DAC block. All simulations work fine in schematic simulations. However, when I did a post layout simulation on DAC block, the result is very bad. In the DAC block, I need a few switches to control the capacitor DAC. When I connect the switch to (...)
I think RC could achieve your goal. You can use a switch res array or switch cap array to tune the frequency.
Dear All, Could you please tell me how to get the mismatch of res or caps by simulation? I am designing a DAC which is composed of res string and cap array, and I can calculate the mismatching of the element according to the formula in the foundry documentation. But I want to run a simulation to verify the calculation result. How to (...)
Hi All, I am looking into design of a SAR ADC . It uses a capacitive DAC . Can someone tell me how should I decide the size of unit capacitor in the capacitor array. I mean it should be 10f 100f 1p ...? please help!!
0.5*2^-8 ≈ 0.2% for the resistor ladder and 0.5*2^-10 ≈ 0.05% for the cap array. Analyze/simulate the postLayout (extracted) netlist. The problem is that most of the "standard" parasitic extraction tools do not guarantee extraction accuracy, they can be easily off by 15-20%. The error can be as high as 100-400
Hello all! I design a 8 bit SAR ADC. 4 MSB bit use binary weighted capacitors, 4 LSB is R-2R ladder. simulation result is OK. But evaluation result is bad. 3 MSB have INL problem. evaluation result: INL 0010 0000 -0.3 LSB 0100 0000
Hi, I am designing a VCO and using the switch capacitor to change the VCO output frequency range. I have a question about the switch capacitor array. I have read some paper about the VCO design, and the circuit they used for switch capacitor is as Figure 1, which contain two capacitor and one switch, but (...)
Ok, I have designed a circuit using a current limiting capacitor in series, driving an array of leds. for 120VAC .47uF 200v cap. It seems to work pretty good. Now I would like to dimm the leds. How can I do this using a dimmer switch that is off the shelf. One way I am considering is by using a rheostat. Will this work? Eda
I need a big 10pF poly-poly capacitor. I saw some capacitor designs where the capacitor is broken down into several smaller ones, even with dummies and a guard ring, some kind of a centroid layout. What's the motif of doing such a thing? Do I need it for my poly capacitor?