Search Engine www.edaboard.com

137 Threads found on edaboard.com: Capacitance Line
Hi, I have a capacitance measurement board which can convert input tiny differential capacitance to voltage. I found a strange thing about it. Whenever I use it to measure constant differential capacitance on weekdays, I can always get stable result as shown below, which is normal. 134128 But every time I use it on w
It could be measurement error. Your scope probe needs to be using tip and barrel only across Vcc and Gnd .... ~ 1cm or less apart without gnd clip. since ESR rises with C, the RC time constant is 10us for LOW ESR and about >>100us for standard. So when cable capacitance is switched current pulse causes a voltage spike at source due to ESR. BIt m
Hi. I want to select a capacitor for a full-bridge rectifier. Load current: Max 20A. Load voltage: Max 400V. line frequency: 85 kHz. Application: Electric vehicle battery charging. How can I calculate the capacitance value? Many thanks.
What will be the load capacitance and resistance?. As you are dealing with a very high Dv/Dt the current will be very high, unless there is no load. Likewise ringing of the pulse due to board wiring and supply decoupling will be a great problem. Frank
Resistance(R) = 150KΩ/m , capacitance(C) = 15.11 pico F/m, Inductance (L)= 1.645?H/m, coupling capacitance (Cc)= 98.59 pico F/m, Mutual Inductance (Lm)= 1.484 ?H/m, I'm guessing the two non-reference conductors are the same physically, as you just have the one value each of C and L. Also, the re
This characteristic is coming from a series resistor (ohmic resistance of the line) and a shunt capacitor (stray capacitance of the line). The only way to improve the pulse response is to minimize this stray capacitance. Stray capacitance is necessary in transmission lines to form (and to (...)
Hi, there are dedicted USB data line protection devices. You need to take care about USB speed. Especially for USB3.0 speed you need very low capacitance diodes. I used VBUS054B (very small) and IP4220CZ6 (TSOP-6 / SOT23-6) for USB2.0 devices. Klaus
Hi! I have a problem with a fabricated RF MEMS capacitors. Theirs capacitance is much (~3 times) less that a calculated value. Could anyone please help me to explain this effect? A capacitor represents a 1-port CPW-line, which ends with a region of a deposited dielectric layer that connects with a ground via cantiliever.
capacitance is the related to size of gap and area between conductors, whereas ESL is attributed to the conductor lengths.
The main effect for your output buffer is the capacitance of the signal line. For an estimation you can use the nearly technology-independent standard value of 0.2 pF/mm , which is valid for global wires of min. size. With this you can estimate its capacitance - and if your output buffer can drive it. Other considerations imply th
Depends on how your present circuit looks like. A partial ground plane may be represented by a coupled lossy inductance plus possibly a parallel capacitance, the feed line as an ideal or lossy transmission line...
You used a quite new version of CST, so unable to open. Recall the definition of z11. it's the input voltage/input current with the output open. Then take a equivalent circuit for your transmission line (easiest: series inductance and parallel capacitance) and voila: real(Z1,1) should almost zero and im(Z1,1) should be some frequency dependent valu
In Step Width Junction discontinuities the effect of the fringing capacitance associated with the wider line of the step discontinuity is similar to an increase in the length of that line. The discontinuity capacitance C that appears due to the discontinuity has the effect of an increase in length of the wide (...)
50Ohm coax it too high capacitance. 100pF/m use 110 ohm Cat5 with pullup/down termination equivalent to 110 to 150 Ohm load and biased to 1.2~1.3 V or two Vbe drops. If using dirty grounds, CM choke like those used for ethernet are needed. Signal swing needs only to be 1Vpp centred on 1.2 but no noise. Thus use UTP cat 5 with 220 to gnd and 27
Have you tried modelling as line (equal to the physical length) with series C? I would simulate two lines of half the ICAP length, and use these S-parameters for de-embedding the line length from the ICAP data (cascade inverse of half length each from left and right side). Then, the remaining response should be the (...)
Estimate it: (input-capacitance_per_bit-cell * no_of_columns) * (1+d) + length_of_bit-line * 0.15 fF/?m d = bit_line_driver_output_capacitance / bit_cells_input_capacitance ≈ 1.2 0.15 fF/?m is the typ. intermediate interconnect (M2) capacitance per ?m length, including fringe (...)
There is a large common mode noise generated with floating SMPS that can be problematic for unbalanced sensitive circuits. e.g. external microphone inputs on laptops. Although primary side grounding reduces conducted noise getting back into the line, there is always a coupling capacitance from primary to secondary coil. When no secondary ground i
Unclear problem specifications bears unclear answers, I fear. I agree that the "If ..." sentence doesn't make much sense. The transformer can be expected to block common mode surges but will pass differential mode surge, if occuring at all. The transformer capacitance passes a certain amount of fast surges, e.g. ESD events to the secondary, so c
How to calculate internal parasitic capacitance of bit line and bit line bar in 6T SRAM using HSPICE?
Show us the signal. The twist pair is typical 120 ohms single ended or 240 differential. It will have a certain distributed capacitance and inductance per foot e.g 10pF/ ft. But more importantly there may be other noise sources of ingress and the line may not be balanced for source and load impedance. Ideally it should be. If you are experienc