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137 Threads found on Capacitance Line
Hi, I have a capacitance measurement board which can convert input tiny differential capacitance to voltage. I found a strange thing about it. Whenever I use it to measure constant differential capacitance on weekdays, I can always get stable result as shown below, which is normal. 134128 But every time I use it on w
It could be measurement error. Your scope probe needs to be using tip and barrel only across Vcc and Gnd .... ~ 1cm or less apart without gnd clip. since ESR rises with C, the RC time constant is 10us for LOW ESR and about >>100us for standard. So when cable capacitance is switched current pulse causes a voltage spike at source due to ESR. BIt m
Hi. I want to select a capacitor for a full-bridge rectifier. Load current: Max 20A. Load voltage: Max 400V. line frequency: 85 kHz. Application: Electric vehicle battery charging. How can I calculate the capacitance value? Many thanks.
What will be the load capacitance and resistance?. As you are dealing with a very high Dv/Dt the current will be very high, unless there is no load. Likewise ringing of the pulse due to board wiring and supply decoupling will be a great problem. Frank
Welcome s.rebelli, By using transmission-line theory in the multiconductor case. What data do you have? Hi I am using transmission line theory for two-conductors. Data: Resistance(R) = 150KΩ/m , capacitance(C) = 15.11 pico F/m, Inductance (L)= 1.645?H/m, co
This characteristic is coming from a series resistor (ohmic resistance of the line) and a shunt capacitor (stray capacitance of the line). The only way to improve the pulse response is to minimize this stray capacitance. Stray capacitance is necessary in transmission lines to form (and to (...)
Hi, there are dedicted USB data line protection devices. You need to take care about USB speed. Especially for USB3.0 speed you need very low capacitance diodes. I used VBUS054B (very small) and IP4220CZ6 (TSOP-6 / SOT23-6) for USB2.0 devices. Klaus
Hi! I have a problem with a fabricated RF MEMS capacitors. Theirs capacitance is much (~3 times) less that a calculated value. Could anyone please help me to explain this effect? A capacitor represents a 1-port CPW-line, which ends with a region of a deposited dielectric layer that connects with a ground via cantiliever.
capacitance is the related to size of gap and area between conductors, whereas ESL is attributed to the conductor lengths.
The main effect for your output buffer is the capacitance of the signal line. For an estimation you can use the nearly technology-independent standard value of 0.2 pF/mm , which is valid for global wires of min. size. With this you can estimate its capacitance - and if your output buffer can drive it. Other considerations imply th
Depends on how your present circuit looks like. A partial ground plane may be represented by a coupled lossy inductance plus possibly a parallel capacitance, the feed line as an ideal or lossy transmission line...
You used a quite new version of CST, so unable to open. Recall the definition of z11. it's the input voltage/input current with the output open. Then take a equivalent circuit for your transmission line (easiest: series inductance and parallel capacitance) and voila: real(Z1,1) should almost zero and im(Z1,1) should be some frequency dependent valu
In Step Width Junction discontinuities the effect of the fringing capacitance associated with the wider line of the step discontinuity is similar to an increase in the length of that line. The discontinuity capacitance C that appears due to the discontinuity has the effect of an increase in length of the wide (...)
Z0 is set by the track geometry and substrate permittivity which changes the inductance and capacitance per length unit respectively. There are calculator for PCB transmission lines, e.g. Adding resistors creates a lossy circuit and isn't the preferred way to change transmission line impedances, but som
Hello, I am trying to extract the capacitance of an interdigitated capacitor along a CPW waveguide. I have been trying different ways, from using Y-parameter by modelling the the thing as a pi-network, however I didn't get something reasonable with the calculated capacitance being heavily frequency dependent, which I guess the inductance of the
Hello, I am simulating a 16x16 sram array(6T) at 45nm technology but i am confused about the value of capacitances of bit line and bit line bar.please help
There is a large common mode noise generated with floating SMPS that can be problematic for unbalanced sensitive circuits. e.g. external microphone inputs on laptops. Although primary side grounding reduces conducted noise getting back into the line, there is always a coupling capacitance from primary to secondary coil. When no secondary ground i
Unclear problem specifications bears unclear answers, I fear. I agree that the "If ..." sentence doesn't make much sense. The transformer can be expected to block common mode surges but will pass differential mode surge, if occuring at all. The transformer capacitance passes a certain amount of fast surges, e.g. ESD events to the secondary, so c
How to calculate internal parasitic capacitance of bit line and bit line bar in 6T SRAM using HSPICE?
Your description doesn't make sense! 1. you say you have 5V DC across 2 wires but it is being toggled off and on at 1000 Bauds. 5V DC is just that, a steady voltage, do you mean it is a serial signal of 5V amplitude? 2. You say there is also a ground wire, is it connected to either of the other wires? 3. On the two '5V' wires, are they carrying