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10 Threads found on edaboard.com: Cascade And Sigma Delta
hello everyone!! I am reading the book "CMOS cascade sigma-delta Modulators for Sensors and Telecom: Error Analysis and Practical Design (Analog Circuits and Signal Processing) Rocío Río Fernández (Author), Fernando Medeiro Hidalgo (Author), Belén Pérez Verdú (Author), (...)
Do you mean Modified CIFF-IF (cascade of Integrators with Weighted FeedForward Summation and Input FeedForward) ?
Hi everyone I met a question in the designing the mash sigmadelta adc. In my design, it is a 2-1-1 mash, every stage has 1-bit flash. I use the scaling factor as in book(cascade sigma delta adc for sensor and telecom). I have finished the schematic, and is (...)
Hello, I want to design 2-2 cascade delta sigma modulator for 2 mhz signal bandwidth, i must sum the two outputs given by the two stages, i use ORCAD PSPICE for similation, i need to implement H(z) =z^-1 which is a delay unit, i don't know the structure of this function using MOS transistors and how i (...)
dear all, does anybody know how I can extract the first stage quantization noise and fedd it into the second stage in hspice? any paper or article?
Can one show me CIC filter(cascade of integrator comb filter) MATLAB code? I want to design a Sinc^2 comb filter followed by sigma-delta ADC. It is 1-bit input , 16-bit output decimation filter. How can I bulit and setting a CIC SIMULINK model? pls help me, thank you!
Hi. guys, I want to design a third-order delta-sigma adc and I want to try MASH(multi-stage noise shaping) structure with 2-1 cascade. The behavioral model is shown below. I have question about the noise cancellation logic. How do I realize the gain block "1/c1" and "b1-1" . I think the two (...)
i simulated sigma-delta modulator in matlab.i am getting same SNR for single stage and cascade stage.can anybody tell me,what may be the problem.i am trying in SD toolbox. why you dont try this toolbox? hope it can help you. Description: The delta-sigma Toolbox includes nearly 100 (...)
hi,all i am a beginer in analog ic design and recently in my first project sigma-delta ADC. my case is: 1 bit, cascade 2-1-1modulator, 64 OSR, in simulink SNR could be 108dB, considering KTC noise/clock jitter/nonideal opamp,SNR could be 97dB, noise level is about -140dB. then i begin my circuit. when (...)
Deal all, I will design 14bit/24MHz sampling 2-2 cascade delta-sigma ADC,Where I should to be careful design rule?stability?or power consumption? About OTA design, How do many unity-bandwidth and settling time enough to satisfy? Design spec: resulation: 14bit input bandwidth: (...)