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17 Threads found on edaboard.com: Cdma Implementation
hello can someone explain how to implement 64 ary orthogonal walsh demodulation in simulink. i need it in cdma reverse link implementation. an urgent reply would be appreciated. 8-)
Hello everybody, I'm a student and i have like topic, Acces Method cdma used in RFID System. Theory side, i can understand the concept, but Simulation side , i dont know how am i going to simulate, and i wanna use Matlab. Can anyone help me to give books, or link for this topic or give an idea about simulating cdma+RFID under Matlab. Thanks
hi everyone.... i am doin a project on cdma transceiver of NoC. can some one tel me what exactly should be the functionality of the network arbiter? basically Network Arbiter? takes charge of informing the requested receiver node to prepare the proper spreading code for decoding and sending a grant signal back to the sender node. can some
Dear debeelab, Thanks for your reply and sharing the code. In your code you are using carrier. I just want to simulate simple DS-cdma for BPSK in AWGN channel. I have written a code and i can decode signals for different users when there is no noise. I am simulating for 8 users and using Walsh code. Now when I simulate using
complete cdma system on FPGA as a project is impossible. You can implement some part of it. Also, you need to do lot of verification and system level design in other ESL softwares. e.g MATLAB, SystemC or others. Addition: Are you planning to implement only cdma algorithm (e.g. PN sequence and scrambling) ?
ANYONE needing help regarding hardware implementation on FPGA is welcome to ask .. mail me
Ashwani the link budget you are looking for is very specific of your implementation and there is no general way to do it. You can take a look at Qizheng Gu book, it's really detailed and cover all the system design of modern transceivers. It is based on a direct conversion cdma design developped at Nokia, but you can easily translate it for y
hi dude i am also doing the same project but i am a month older so i can help what i have inferred so far buy a SPARTAN 3A(1800DSP EDITION) kit its the most economical and optimal option then you have to follow these steps study cdma generate its algorithm for transciever on simulink convert it into system generator(XILINX ISE) implement on y
Hi dear Ahmad you could you xilinx cores for the FFT and cyclic prefix for the OFDM system, also you could use PN generatot cores of cdma. I used spartan 3A , it was good and cheap. if you want more details tell me.
for this block diagram can u help me to draw circuit diagram...p
Hi, Any body have an document on 6 sector site implementation in cdma. Please share with us. Rgds
i have posted one.. "Application of adaptive filtering in cdma.." infact if u giv me ur id..i can send u more projects..:D:D Added after 1 minutes: another one is: study and implementation of multiraste dsp for sdr..." plz download it...
Hi guyz ... i wish to do a final year project abt cdma or Wcdma but i dont want it to be just simulations ... i want to implement it ... i need ur help abt any ideas and what to implement ??? Thanks in advance
Hi .I want to do some sort of implementation of cdma I hope you people can give me some useful ideas as to what are the recent trends in this field and what sort of project will be suitable for undergraduate level(Final year project). The project should preferrably on MC-cdma.Any additional help will be appreciated.Mere simulation project ar
i have decided to work on cdma for my final year project... so any body can please help me out in deciding the topic for that... well, I did my master thesis on "Investigation and FPGA implementation of predistortion for future UMTS LINC Transmitter". It is linearisation method and currently hot topic in 3G industry as we
I have worked on FPGA and ADSP on the cdma technologies. An FPGA can support a significantly higher data rate than the DSP for obvious reasons. I know of an implementation on a TI processor that supported 19.6kBps.
I have worked on FPGA and ADSP on the cdma technologies. An FPGA can support a significantly higher data rate than the DSP for obvious reasons. I know of an implementation on a TI processor that supported 19.6kBps.