Search Engine **www.edaboard.com**

98 Threads found on edaboard.com: **Cic And**

can any1 please give me a sample vhdl code for **cic** decimation filter please.
thankyou,
maya

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-30-2013 09:30 :: mayaraj :: Replies: **3** :: Views: **1182**

What does it mean - z = 2y ?
To multiply use * symbol.
For upsample or downsample use 'upsample' or 'downsample' comm**and**s.
Or design an interpolation or decimation FIR or **cic** filter.

Digital Signal Processing :: 12-22-2012 06:25 :: Mityan :: Replies: **2** :: Views: **1132**

Dear all,
I want to design a **cic** decimation filter for a 3rd-order sigma-delta modulator with single-bit quantization.*As we know, **cic** filter need's 2's complement arithmetic. Let's assume I need 16 bits internal word length for correct operation.
Now my question is, do I need to convert my 1-bit unsigned quantized data (at the the modulator

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-04-2012 06:05 :: bardia :: Replies: **3** :: Views: **1992**

A **cic** decimator with power-of-two ratio R will keep the most significant bits **and** add less significant bits according to the useable dynamic range. If we imagine a fractional number representation, this corresponds to a gain of 1. Bit pruning is just the method to derive the required bit number of each stage after deciding about the output word wid

ASIC Design Methodologies and Tools (Digital) :: 10-26-2012 21:19 :: FvM :: Replies: **10** :: Views: **2720**

what are the advantages of integrating at higher sampling rate **and** for comb filters lower sampling rate in **cic** filters

Digital Signal Processing :: 09-05-2012 06:25 :: kannan2590 :: Replies: **2** :: Views: **1006**

Hi, I have two simple question to ask
why doesn't the layout instance of MOS from **cic** library(0.35um) have bulk contact?
I have only see diff **and** nimp for nmos but no pimp
**and** how do I choose the contact type in calibre? ex: M1_POLY1 ,M1N,M1P...
thank you

Analog Circuit Design :: 08-22-2012 14:33 :: l123419881021 :: Replies: **0** :: Views: **535**

Hey everyone,
I wrote a code for a **cic** filter using Verilog HDL. However, I do not know if my problem lies in the testbench I have written or in Multisim. I would appreciate it if someone could tell me if something is wrong in the following short test bench.
module test;
reg clk;
wire x,y;
assign x=8'b 00000001;
wb_hp_f (.clk(clk),.

ASIC Design Methodologies and Tools (Digital) :: 07-22-2012 13:58 :: H.Hachem :: Replies: **16** :: Views: **2539**

Hi,
I'm currently writing my bachelor's thesis. I read many research papers **and** came up with a very efficient **and** fast FIR filter structure. However, yesterday I received the parameters of the filter needed at the institute in order to program it on an FPGA. **and** to my surprise, they need a high-pass filter with a pass (...)

Digital Signal Processing :: 07-11-2012 17:34 :: H.Hachem :: Replies: **3** :: Views: **3481**

Hi ALL
in now days i design FIXED POINT FIR that wil be implemented on FPGA
the filtering unit using **cic** decimation followed by 2 fir LPF.
the input to the unit is 32 bits - 30 fractions **and** 2 for real number.
the end of the unit in 57 bits **and** i take just the fractions -51 downto 22.
when i analyze the FILTER FREQUENCY RESPONSE (...)

Digital Signal Processing :: 05-06-2012 07:26 :: itmr :: Replies: **0** :: Views: **797**

Hi all!
I am trying to design a simple **cic** decimation filter for my first order delta sigma modulator. Oversampling is 1024 **and** output is 1 bit. I tried to go with the st**and**ard theory for design. It gives 11 bits for 1st integrator, **and** 21 for the next. I am amazed over the fact that how can a 21 bit output be obtained (...)

Analog Circuit Design :: 03-22-2012 11:22 :: juneja :: Replies: **12** :: Views: **1391**

The concepts behind FIR design are very well known. In reality, an FIR filter is known as an inner-product. It is so well defined that efficient methods are very well known -- **cic** **and** half-b**and**. Further, it isn't even difficult to turn a least-squares "reduced basis" into a filter. Several "window functions" exists for those who don't (...)

Digital Signal Processing :: 03-03-2012 07:32 :: permute :: Replies: **2** :: Views: **849**

hi all
i design now decimation unit to downsample signal samplesd in 1M to 2K
i cascaded **cic** decimation then fir decimation **and** then downsample block ( in simulink).
when i simulate the unit it looks good - i mean i can see the filter gain ( when the input is pulse) **and** i see the down sampling when the input is sin wave sampled by (...)

Digital Signal Processing :: 02-20-2012 07:48 :: itmr :: Replies: **0** :: Views: **1235**

Elementary Electronic Questions :: 12-28-2011 12:32 :: FvM :: Replies: **2** :: Views: **819**

Hi ALL
I working on aplication that i need to sample 1.9Khz signal by 1Mhz , its mean 512 OSR - AFTER SIGMA DELTA MODULATION ( FOR SEPARATE the quantization noise from the signal) i need to decimate the signal by decimatin rate of 512.
i decided to use **cic** filter to decimate by 128 **and** then cascade more 2 FIR - one as compensator **and** (...)

Digital Signal Processing :: 11-20-2011 15:45 :: itmr :: Replies: **1** :: Views: **1342**

Hi ALL
I working on some application that gonna be implement on FPGA
It involve with sample signal by 512 over sampling ratio **and** then decimate the signal by this OR - 512 (DELTA SIGMA MODULATION)
does some one have a good idea for me about the decimation filter block
i thought about 3 options-
1 - **cic** DECIMATE BY 128 **and** THEN (...)

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-25-2011 13:37 :: itmr :: Replies: **0** :: Views: **934**

HI ALL
i am working now on some delta sigma application - i overasample the digital input signal by 512 then pass it through delta sigma modulator **and** then i need to decimate it (by 512)
because i need to implement it on FPGA i thought to use **cic** DECIMATION FILTERS to decimate by 256 **and** then use fir to decimate by 2 (...)

Digital Signal Processing :: 10-06-2011 14:25 :: itmr :: Replies: **0** :: Views: **1137**

Read the error messages more thoroughly. The syntax error is in the component code, not the test bench.
entity **cic** is
generic(CI_SIZE : integer := 18; -- **cic** input data width
CO_SIZE : integer := 30; -- **cic** output data width
STAGES : integer := 5);
port( -- This line is missing
ce : in std_logic

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-02-2011 21:33 :: FvM :: Replies: **13** :: Views: **3720**

There's some code involved like **cic** filter, FIR filter, IIR filter ,Cordic algorithm **and** FFT in the book "Digital Signal Processing with Field Programmable Gate Arrays".Hope it would be helpful.

ASIC Design Methodologies and Tools (Digital) :: 09-16-2011 05:27 :: rockybc :: Replies: **2** :: Views: **1023**

Hi,
Some question regarding digital low pass filter for ADC.
If I need 12 ENOB output do I have to implement dcimation filter (**cic**) with decimation factor at least 4096? **and** ENOB **and** stable output bits are the sam

Microcontrollers :: 08-11-2011 10:15 :: Tivgar :: Replies: **1** :: Views: **753**

about delta sigma **cic** filter
it consists of integrator , decimator **and** differentiator.
lots of thesis discuss the mininmun word length for preventing overflow.
**and** it says that it is the same as the average window filter in frequency domain.
but if we disuss it in transient domain?
since every integrator in each stage will (...)

Analog Circuit Design :: 07-17-2011 06:53 :: pianomania :: Replies: **3** :: Views: **2144**