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98 Threads found on edaboard.com: **Cic And**

Digital Signal Processing :: 07-02-2011 03:44 :: permute :: Replies: **1** :: Views: **1325**

i am trying to design a decimator for sigma delta converter . my decimation factor is 48. from material i found i decided on a **cic** filter for first stage (decimation of 24) **and** a **cic** filter as second(decimation of 2).
sampling freq =3840 KHZ
Fin = fin = 0-80khz
stop b**and** attenuation = 100 dB
About the SINK filter (...)

Digital Signal Processing :: 04-24-2011 18:35 :: fasto2008 :: Replies: **0** :: Views: **1612**

Hi,
I have designed a decimator filter for a 8 bit sigma-delta ad convertor. I use one **cic**, one halfb**and** **and** one FIR filter. The output of the decimator is 38 bits. In order to achieve lower power consumption I dont want to cut all 30 LSB bits at the end. Instead of this I want to reduce the output for each stage. For example cutting 5 bits (...)

Digital Signal Processing :: 03-22-2011 15:15 :: feyza_ :: Replies: **0** :: Views: **796**

i am trying to design a decimator for sigma delta converter for audio. my decimation factor is 128. from material i found i decided on a **cic** filter for first stage (decimation of 64) **and** a half b**and** FIR as second.
so the **cic** filter has 3 parameters - decimation factor , no of delay elements **and** the (...)

Digital Signal Processing :: 02-11-2011 20:42 :: steadymind :: Replies: **6** :: Views: **2053**

Hi,
I want to design a **cic** filter which has a decimation ratio of 32, I need 10 bits at the output, **and** my input is 2 bits, I want 3 stages **and** differential delay is 1 so according to Hogenauer's paper wordlength is N*log(RM)+Bin -1=3*log(32)+2=16 bits, however I want 10 bits at the output, **and** again according to (...)

Digital Signal Processing :: 01-20-2011 13:27 :: bittersweet :: Replies: **1** :: Views: **1436**

Usually, you'll want to utilize the delay register to achieve pipeline action **and** connect the next stage at it's output rather than at the adder directly.
A separate pipeline register may be used, if the **cic** integrator clock is as divided system clock.

ASIC Design Methodologies and Tools (Digital) :: 07-03-2010 15:29 :: FvM :: Replies: **4** :: Views: **1248**

Hi all,
Lst say a input signal IP with 0~200KHz bw is sampled at fs=16MHz (lets call it X), then pass through a 1st order **cic** decimation filter (R=8, M=1) to get 2MHz output (lets call it Y).
Let define Δf as shifting the signal to center at f, so
X = IPΔ0 + IPΔ16M + IPΔ32M ...
**and** sinc is the sinc function without al

Digital Signal Processing :: 07-03-2010 13:44 :: gggould :: Replies: **0** :: Views: **875**

I am designing a two stage filter to do decimation at the output of a Sigma Delta modulator. Here is the spec -
Sampling frequency - Fs - 1.4MHz
Decimation factor - D - 100
Output resolution - 13 bits.
The filter, **and** the modulator is reset every 100 clock cycles.
To accomplish this, I used a 5 stage **cic** filter to decimate by 20 for the

ASIC Design Methodologies and Tools (Digital) :: 06-24-2010 18:40 :: analog_fever :: Replies: **0** :: Views: **843**

sinc3 vs **cic**:
guess it is a trade-off between complexity **and** performance. More complex -> better image removal **and** vice versa.
slope to magnitude:
all these filters do are just averaging. More complex filters given you average of the averages many times over. Now finding the average is just integration, if you ignore the scaling by (...)

Digital Signal Processing :: 02-10-2010 13:19 :: bulx :: Replies: **3** :: Views: **1353**

I am working on a Sigma Delta ADC project, **and** need to decide the bit-width of the digital filter. My filter has 4 stages, the first is **cic** **and** the bit width is 29 bits according to the OSR. My final filter output is only 24 bits. So this means the other 3 FIR filters need to reduce 5 bits in total. If my input is 4-bits signed (...)

Digital Signal Processing :: 07-25-2009 12:25 :: eebug :: Replies: **0** :: Views: **924**

when using the **cic** filter as decimation filter,is a compesation filter needed?
the basic **cic** structure is composed of two section,integrator section **and** comb section.I found that the response of integrators for dc input is without bound. so does that imply we can not use the structure in practice?

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 07-06-2009 03:59 :: longqingshan :: Replies: **2** :: Views: **925**

My IF is 5Mhz.
I need to reduce my sampling frequency 409.8Mhz to 20.48 Mhz by using FIR lowpass filter, so i am decimating it in 2 stages , first time i am using **cic** filter **and** decimation factor 5 then i will get the new sampling frequency 81.9 which is given to half b**and** filter by decimating factor 4 then we will obtain finally (...)

Digital Signal Processing :: 06-21-2009 09:33 :: guest_1044 :: Replies: **0** :: Views: **2201**

Hi,all
I am in a project of Sigma-Delta ADC. But I get in trouble when I design the digital filter in the MATLAB. The filter consists of a **cic**, a **cic**COMP **and** two halfb**and**. When **cic** is followed by the **cic**COMP **and** then the twe halfb**and**s, the (...)

Digital Signal Processing :: 05-12-2009 15:29 :: wqy1985 :: Replies: **6** :: Views: **2275**

I have designed sigma-delta followed by **cic** decimator ,
**and** run FFT at **cic** filter output.
The result is shown in attachment file.
what's wrong in the spectrum??
thank you!
-------------------------
spec:
fin=1.5625 Hz
fs=51200 Hz
decimator ration=256

Digital Signal Processing :: 04-16-2009 10:27 :: kuohsi :: Replies: **5** :: Views: **1469**

I have designed sigma-delta followed by **cic** decimator ,
**and** run FFT at **cic** filter output.
The result is shown in attachment file.
what's wrong in the spectrum??
thank you!
-------------------------
spec:
fin=1.5625 Hz
fs=51200 Hz
decimator ration=256

Analog Circuit Design :: 04-16-2009 08:25 :: kuohsi :: Replies: **0** :: Views: **726**

Can one show me **cic** filter(cascade of integrator comb filter) MATLAB code?
I want to design a Sinc^2 comb filter followed by sigma-delta ADC.
It is 1-bit input , 16-bit output decimation filter.
How can I bulit **and** setting a **cic** SIMULINK model?
pls help me, thank you!

Analog Circuit Design :: 04-03-2009 02:54 :: kuohsi :: Replies: **2** :: Views: **6950**

Hello everyone,
Can anyone let me know what is the best decimator filter structure to achieve low latency compare to the tradisional **cic** filter with cascade Comb **and** integrator section?
Thanks.

Digital Signal Processing :: 03-10-2009 03:53 :: cafukarfoo :: Replies: **3** :: Views: **3050**

Hi Sir/Madam,
I had done an evaluation using
1. **cic** filter with decimator factor of 128
2. **cic** filter with decimator factor of 32 **and** 2 half b**and** filter.
I am seeing the time needed for the filter to get stable is longer for option 2 above.
What i did is i run a step response for filter option 1 (...)

Digital Signal Processing :: 02-27-2009 07:36 :: cafukarfoo :: Replies: **2** :: Views: **2328**

Hi Sir/Madam,
Can anyone here let me know why the amplitude of the signal get distorted after it go through the **cic** filter?
Is is due to the passb**and** of the **cic** filter is not flat?
I had try to cascade the **cic** filter with compensator filter **and** i see the passb**and** quite flat (+/- (...)

Digital Signal Processing :: 02-26-2009 09:35 :: cafukarfoo :: Replies: **5** :: Views: **1128**

you can download some paper from IEEE which can help you much.
An economical class of digital filters for decimation **and** interpolation.pdf
This paper is a good paper **and** it introduces **cic** filter first.

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-15-2008 01:52 :: radar08 :: Replies: **1** :: Views: **1422**

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crossover frequency | dumpfile | tcl tutorial | dynamic load | loop gain spice | crystal model | pic basic program | clock gate timing | tree multiplier | walking