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98 Threads found on Cic And
Hi, I am designing a decimation filter for sigma delta ADC. I have read some materials, and my design consists of 3-stages. 1 cic filter, 1 cic compensator and 1 halfband filter, with oversampling rate 128, input bitstream (1 bit). The output will be 16bit. I designed the filter in MATLAB, (...)
Hi all, I need to implement a cic decimator in an FPGA in fixed-point format. Everything works fine in floating point format in Matlab simulations. I am now translating the design from floating point to fixed point, and have to design the bit width of each integrator and differentiator. I know the bitwidth at output can be calculated (...)
how to decide the bits of the decimation filer (cic filter)??? if my sigma delta adc is two stage (one bit),and decimation rate is 256. thanks advance!!!!
you can get interpolator, decimator and similar filter (cic) structure.... in both verilog and VHDL codings in DSP with FPGA - Meyer Besse.
i followed the simulink demo'dspsdadc' in R14 and try to modify the first FIR Decimation to cic Decimation.some errors was reported when i started the simultion.but i have no idea about could you help me?
Cascaded Integrator-Comb (cic): a cascaded integrator-comb (cic) is an efficient implementation of an interpolator (which increases the sample rate of a signal) or decimator (which decreases the sample rate), typically used in FPGA architectures. Contrary to the name, a cic filter is a combination of a
hi, would you please introduce me a good reference for learning digital upconversion in fpga? i mean about cascading of pulse shaping filter and cic interpolators... (((i dont know what's wrong withh this post? dear cleaner, at least tell why!!)))
is there any explicit formulas for design of cic filters i mean as long as i've seen there is no formulas for cutoff frequency and stopband determination. should i decide by Trial and error? how should i decide for M,N,R(cic parameters)?!!
can any one suggest how to get impulse response of three stage cic filter implemented in vlsi.
Hi, I'm using cadence composer to design circuit and hspice to run simulation, but how to embed hspice to the composer window? Thanks for your help! Regards, Joffre
Hello all, Installed Fedora5, trying to run Cadence cic tool and having issues with LMGRD This is the error message, I am kind of stuck :cry: any help is appreciated /CadenceTools/tools/bin/lmgrd: relocation error: /CadenceTools/tools/bin/lmgrd: symbol errno, version GLIBC_2.0 not defined in file with link time referenc
i am designing qpsk demodulator,which requirement as follows: data bit rate 36Mbit/s, sample frequency 115MHz; i am like to use cic ,HB and PFIR to decrease data rate and shaping date. i want to know how to arrange cic hb and pfir decimate rate? or someone can give (...)
hello every: i am beginner of digital filter design. i am designing qpsk modulator/demodulator, i am like to know which construction is better for shaping filter,cic filter and HB filter by fpga . best regard! Mr.Z
no one cant send pdf for document for ur design. only u can get encounter userguide from or best of luck
if you know "chinese" have some document about P&R
Sorry, I am a green hand here . what is cic filter? and what is its application? thanks a lot!!
better good idea about read cic training materials and synopsys solvnet . both gives better idea, go throu it.
hi, go to and maybe you can find some tutorial.
Search in google first.There have good thing you need. If your application is ADC,then cic followed FIR is the common structure.
cic course is a good start. Added after 1 minutes: