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59 Threads found on edaboard.com: Cic Decimation
The question is still unclear. Do you want sinc^n filters without decimation? Or implement cic? As you should know from literature, transfer function of a cic decimator isn't exactly sinc rather than the quotient of two sine^n functions which approaches sinc^n for large decimation factors.
How to realize a sinc function using cic filter for decimation and interpolation ??? Can I combine interpolation and decimaton methods inorder to get the complete response of a sinc function???
How to realize a sinc function using cic filter for decimation and interpolation ??? Can I combine interpolation and decimaton methods inorder to get the complete response of a sinc function???
Hello, I?ve got problem with my 3 Stage Filter Design in MATLAB (for a Delta-Sigma Modulator), it would be great if someone could help! The delta-sigma modulator has an input signal of 1kHz and wir OSR = 512 an output of 1 MHz. So I decided to do a 3 stage Filter: cic w. 1 Bit input (decimation factor R = 128), cic Compensator (...)
The question title involves a contradiction in terms, because a cic decimator is a filter with finite impulse response as well. So more exactly you are asking about using different FIR characteristics than cic as a decimation filter. The general answer is quite simple, if you want a different frequency characteristic than (sin(x)/x)^n, (...)
Hi, I am trying to realize a cic decimation filter (for delta-sigma ADC) in Verilog. I want to know whether to use NON-BLOCKING ASSIGNMENT <= or BLOCKING ASSIGNMENT = in Verilog implementation of the constituent integrators and differentiators. E.g., for the integrator section (image below), commonly cited code is like: [AT
hi i am designing a sigma delta adc. \can i keep a osr which is not in powers of 2 eg. 50. will i be able to design a decimation/\cic filter for such a decimation factor?? or is it necesaary to keep \osr in powers of 2???
In a three stage cic filter and the decimation factor is 32 , does it means that overall decimation is 32*32*32 ( 32768 )or just 32 only? - - - Updated - - - I search the google found it only 32. For dso in fixed 100MHz sampling clock to adc , can I achieve lower the sampling rate like selecting 1ms , 5m
my ADC was 1 bit modulator so I am confused for multibits data (after decimation)Do you understand decimation filter ? Most simple decimation filter is cic filter. Frequency characteristic of cic filter is same as moving averaging filter. Output d
Hello Everyone, Delta Sigma ADC: Modulator = 2nd Order cic Filter = 3rd Order OSR = 256 cic is hardware efficient decimation Filter but its frequency response shows passband droop and wide transition band, so my question is due to these non-idealities of cic filter, How much degradation in SNR occur and theory (...)
step 1: try yourself. step 2: post results. step 3: ask specific questions about specific problems. Good luck with your homework! Nono, don't bother replying how unhelpful that was. Expend your keystrokes instead on googling for "cic decimation HDL" and such.
What does it mean - z = 2y ? To multiply use * symbol. For upsample or downsample use 'upsample' or 'downsample' commands. Or design an interpolation or decimation FIR or cic filter.
cic don't particularly need two's complement, because signed/unsigned is only a matter of number interpretation for addition and substraction. You can implement it either with unsigned or signed arithmetic. The data coding can be converted at the output, e.g. from offset binary to two's complement by inverting the MSB. In other word, do
Dear all, I want to design a cic decimation filter for a 3rd-order sigma-delta modulator with single-bit quantization. As we know, cic filter need's 2's complement arithmetic. Let's assume I need 16 bits internal word length for correct operation. Now my question is, do I need to convert my 1-bit unsigned quantized data (at the (...)
Hello, I'm trying to calculate the gain of a cic decimation filter after bit pruning. I believe bit pruning affects the gain because it is not possible to represent the factor (RM)^N with the limited output precision. Any help will be appreciated
Linear phase is in fact a well defined term (other than phase change). Strictly spoken, only FIR filter with symmetrical impulse response expose linear phase (respectively constant group delay). cic decimators belong to this class of FIR filters.
Hi, I'm currently writing my bachelor's thesis. I read many research papers and came up with a very efficient and fast FIR filter structure. However, yesterday I received the parameters of the filter needed at the institute in order to program it on an FPGA. And to my surprise, they need a high-pass filter with a pass band from 10Hz to 1MHz! Wh
Hi ALL in now days i design FIXED POINT FIR that wil be implemented on FPGA the filtering unit using cic decimation followed by 2 fir LPF. the input to the unit is 32 bits - 30 fractions and 2 for real number. the end of the unit in 57 bits and i take just the fractions -51 downto 22. when i analyze the FILTER FREQUENCY RESPONSE ( for t
Hi all! I am trying to design a simple cic decimation filter for my first order delta sigma modulator. Oversampling is 1024 and output is 1 bit. I tried to go with the standard theory for design. It gives 11 bits for 1st integrator, and 21 for the next. I am amazed over the fact that how can a 21 bit output be obtained when the modulator itself
hi all i design now decimation unit to downsample signal samplesd in 1M to 2K i cascaded cic decimation then fir decimation and then downsample block ( in simulink). when i simulate the unit it looks good - i mean i can see the filter gain ( when the input is pulse) and i see the down sampling when the input is sin (...)