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59 Threads found on edaboard.com: **Cic Decimation**

The question is still unclear. Do you want sinc^n filters without **decimation**? Or implement **cic**?
As you should know from literature, transfer function of a **cic** decimator isn't exactly sinc rather than the quotient of two sine^n functions which approaches sinc^n for large **decimation** factors.

Digital Signal Processing :: 01-25-2017 09:15 :: FvM :: Replies: **4** :: Views: **871**

How to realize a sinc function using **cic** filter for **decimation** and interpolation ??? Can I combine interpolation and decimaton methods inorder to get the complete response of a sinc function???

Digital Signal Processing :: 01-25-2017 07:35 :: GayathriN :: Replies: **0** :: Views: **1**

How to realize a sinc function using **cic** filter for **decimation** and interpolation ??? Can I combine interpolation and decimaton methods inorder to get the complete response of a sinc function???

Digital Signal Processing :: 01-25-2017 07:24 :: GayathriN :: Replies: **0** :: Views: **3**

Hello,
I?ve got problem with my 3 Stage Filter Design in MATLAB (for a Delta-Sigma Modulator),
it would be great if someone could help!
The delta-sigma modulator has an input signal of 1kHz and wir OSR = 512 an output of 1 MHz.
So I decided to do a 3 stage Filter: **cic** w. 1 Bit input (**decimation** factor R = 128), **cic** Compensator (...)

ASIC Design Methodologies and Tools (Digital) :: 09-21-2016 13:29 :: hyperbolicus :: Replies: **0** :: Views: **913**

The question title involves a contradiction in terms, because a **cic** decimator is a filter with finite impulse response as well.
So more exactly you are asking about using different FIR characteristics than **cic** as a **decimation** filter. The general answer is quite simple, if you want a different frequency characteristic than (sin(x)/x)^n, (...)

Digital Signal Processing :: 05-31-2015 08:50 :: FvM :: Replies: **1** :: Views: **1280**

Hi,
I am trying to realize a **cic** **decimation** filter (for delta-sigma ADC) in Verilog.
I want to know whether to use NON-BLOCKING ASSIGNMENT <= or BLOCKING ASSIGNMENT = in Verilog implementation of the constituent integrators and differentiators.
E.g., for the integrator section (image below), commonly cited code is like:
[AT

PLD, SPLD, GAL, CPLD, FPGA Design :: 03-31-2015 15:23 :: jdp721 :: Replies: **10** :: Views: **2636**

hi
i am designing a sigma delta adc. \can i keep a osr which is not in powers of 2 eg. 50. will i be able to design a **decimation**/\**cic** filter for such a **decimation** factor?? or is it necesaary to keep \osr in powers of 2???

Analog Circuit Design :: 12-01-2014 12:25 :: pankaj jha :: Replies: **0** :: Views: **486**

In a three stage **cic** filter and the **decimation** factor is 32 , does it means that overall **decimation** is 32*32*32 ( 32768 )or just 32 only?
- - - Updated - - -
I search the google found it only 32. For dso in fixed 100MHz sampling clock to adc , can I achieve lower the sampling rate like selecting 1ms , 5m

PLD, SPLD, GAL, CPLD, FPGA Design :: 07-12-2014 11:47 :: lgeorge123 :: Replies: **1** :: Views: **900**

my ADC was 1 bit modulator
so I am confused for multibits data (after **decimation**)Do you understand **decimation** filter ?
Most simple **decimation** filter is **cic** filter. Frequency characteristic of **cic** filter is same as moving averaging filter.
Output d

Digital Signal Processing :: 08-05-2013 17:19 :: pancho_hideboo :: Replies: **3** :: Views: **1073**

Hello Everyone,
Delta Sigma ADC:
Modulator = 2nd Order
**cic** Filter = 3rd Order
OSR = 256
**cic** is hardware efficient **decimation** Filter but its frequency response shows passband droop and wide transition band, so my question is due to these non-idealities of **cic** filter, How much degradation in SNR occur and theory (...)

Digital Signal Processing :: 04-09-2013 10:14 :: Eminent.Engineer :: Replies: **1** :: Views: **1850**

step 1: try yourself.
step 2: post results.
step 3: ask specific questions about specific problems.
Good luck with your homework!
Nono, don't bother replying how unhelpful that was. Expend your keystrokes instead on googling for "**cic** **decimation** HDL" and such.

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-30-2013 09:35 :: mrflibble :: Replies: **3** :: Views: **1165**

What does it mean - z = 2y ?
To multiply use * symbol.
For upsample or downsample use 'upsample' or 'downsample' commands.
Or design an interpolation or **decimation** FIR or **cic** filter.

Digital Signal Processing :: 12-22-2012 06:25 :: Mityan :: Replies: **2** :: Views: **1126**

PLD, SPLD, GAL, CPLD, FPGA Design :: 12-04-2012 06:39 :: FvM :: Replies: **3** :: Views: **1972**

Dear all,
I want to design a **cic** **decimation** filter for a 3rd-order sigma-delta modulator with single-bit quantization.
As we know, **cic** filter need's 2's complement arithmetic. Let's assume I need 16 bits internal word length for correct operation.
Now my question is, do I need to convert my 1-bit unsigned quantized data (at the (...)

Digital Signal Processing :: 12-04-2012 03:56 :: bardia :: Replies: **1** :: Views: **1207**

Hello,
I'm trying to calculate the gain of a **cic** **decimation** filter after bit pruning. I believe bit pruning affects the gain because it is not possible to represent the factor (RM)^N with the limited output precision.
Any help will be appreciated

ASIC Design Methodologies and Tools (Digital) :: 10-26-2012 20:45 :: H.Hachem :: Replies: **10** :: Views: **2697**

Linear phase is in fact a well defined term (other than phase change). Strictly spoken, only FIR filter with symmetrical impulse response expose linear phase (respectively constant group delay). **cic** decimators belong to this class of FIR filters.

PLD, SPLD, GAL, CPLD, FPGA Design :: 10-26-2012 13:34 :: FvM :: Replies: **5** :: Views: **698**

Hi,
I'm currently writing my bachelor's thesis. I read many research papers and came up with a very efficient and fast FIR filter structure. However, yesterday I received the parameters of the filter needed at the institute in order to program it on an FPGA. And to my surprise, they need a high-pass filter with a pass band from 10Hz to 1MHz! Wh

Digital Signal Processing :: 07-11-2012 17:34 :: H.Hachem :: Replies: **3** :: Views: **3455**

Hi ALL
in now days i design FIXED POINT FIR that wil be implemented on FPGA
the filtering unit using **cic** **decimation** followed by 2 fir LPF.
the input to the unit is 32 bits - 30 fractions and 2 for real number.
the end of the unit in 57 bits and i take just the fractions -51 downto 22.
when i analyze the FILTER FREQUENCY RESPONSE ( for t

Digital Signal Processing :: 05-06-2012 07:26 :: itmr :: Replies: **0** :: Views: **792**

Hi all!
I am trying to design a simple **cic** **decimation** filter for my first order delta sigma modulator. Oversampling is 1024 and output is 1 bit. I tried to go with the standard theory for design. It gives 11 bits for 1st integrator, and 21 for the next. I am amazed over the fact that how can a 21 bit output be obtained when the modulator itself

Analog Circuit Design :: 03-22-2012 11:22 :: juneja :: Replies: **12** :: Views: **1358**

hi all
i design now **decimation** unit to downsample signal samplesd in 1M to 2K
i cascaded **cic** **decimation** then fir **decimation** and then downsample block ( in simulink).
when i simulate the unit it looks good - i mean i can see the filter gain ( when the input is pulse) and i see the down sampling when the input is sin (...)

Digital Signal Processing :: 02-20-2012 07:48 :: itmr :: Replies: **0** :: Views: **1232**

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