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113 Threads found on edaboard.com: Cic Filter
Consider Frequency response of Moving Average filter is Sinc. Moving Average filter or cic filter is a most simple LPF.
Hi Altruists, I need to design an incremental sigma delta ADC (OSR=500) where I need to implement a CoI filter. From literature study i found that this CoI filter is actually same as cic but without the comb part for cic. I need to write a code in Verilog (or Verilog A) for CoI filter. I dont have so much (...)
is an encrypted file used for synthesis only and can be simulated. The simulation need to use the dedicated simulation model generated along with the synthesizable core.
The question is still unclear. Do you want sinc^n filters without decimation? Or implement cic? As you should know from literature, transfer function of a cic decimator isn't exactly sinc rather than the quotient of two sine^n functions which approaches sinc^n for large decimation factors.
How to realize a sinc function using cic filter for decimation and interpolation ??? Can I combine interpolation and decimaton methods inorder to get the complete response of a sinc function???
How to realize a sinc function using cic filter for decimation and interpolation ??? Can I combine interpolation and decimaton methods inorder to get the complete response of a sinc function???
i read few articles and i didn't find any criteria for deciding N Sounds like you missed a basic introduction to cic decimators. The number of stages N is the filter order, you can visualize it's effect by looking at the cic response either in time or frequency domain. In frequency domain, the magnitude characteristic is approximate
Hello, I?ve got problem with my 3 Stage filter Design in MATLAB (for a Delta-Sigma Modulator), it would be great if someone could help! The delta-sigma modulator has an input signal of 1kHz and wir OSR = 512 an output of 1 MHz. So I decided to do a 3 stage filter: cic w. 1 Bit input (decimation factor R = 128), (...)
Dear all, I wanted to know is the cic filter implemented in open core example. Is this a combination of registers and adder ? IS it a example for loopy structure ? Please let me know. Thank you
The question title involves a contradiction in terms, because a cic decimator is a filter with finite impulse response as well. So more exactly you are asking about using different FIR characteristics than cic as a decimation filter. The general answer is quite simple, if you want a different frequency characteristic than (...)
I want to know if I can use Blocking assignment = instead of <= above - shouldn't that be better? Apart from the problem explained by ads-ee. why do you think the blocking variant should be better? It replaces the regular cic integrator part by a different circuit. It reduces the propagation delay by two clock cycles at cost of maxi
Hello Everyone, I am designing cic filter, I have one doubt, how we choose no. of sections of comb and integrator
hi i am designing a sigma delta adc. \can i keep a osr which is not in powers of 2 eg. 50. will i be able to design a decimation/\cic filter for such a decimation factor?? or is it necesaary to keep \osr in powers of 2???
I believe both another forum member and I responded to this post, but now that it has been moved it no longer has those responses and a search didn't come up with any other similar posts for cosine DDS that matches the original post. What is the point of moving threads if it corrupts the integrity of subsequent responses?
In a three stage cic filter and the decimation factor is 32 , does it means that overall decimation is 32*32*32 ( 32768 )or just 32 only? - - - Updated - - - I search the google found it only 32. For dso in fixed 100MHz sampling clock to adc , can I achieve lower the sampling rate like selecting 1ms , 5m
I am studying the use of decimation filters in Sigma Delta modulators. While simulating I came across an unusual result. i) I have an ideal 2nd order 1-bit (OSR=2048) sigma delta modulator. The SNR of its output is 145dB. ii) I passed the modulators output through the first cic filter (decimation factor = 64, no. of sections=3, (...)
Hello all, I am trying to make cic filter using VHDL and will implement it on FPGA. I could design a cic filter with the output from comb part does not overflow, but it DOES overflow in integrator part. From some documents and my result, I know the overflow of integrator does not influence the final output. However, (...)
my ADC was 1 bit modulator so I am confused for multibits data (after decimation)Do you understand decimation filter ? Most simple decimation filter is cic filter. Frequency characteristic of cic filter is same as moving averaging filter. Output d
hello all , I need to implement cic decimator, here is the matlab code using fvtool r=64; m=1; n=3; iwl=16; owl=12; IFL = 0; % Input fraction length cic = mfilt.cicdecim(r,m,n); cic.InputFracLength = IFL; f_in =5120; h=fvtool(cic,'FS',f_in); I checked the impulse response using the fvtool (...)
hello all , I have a problem when designing cic filter on matlab here is the code : r=64; m=1; n=3; IFL = 0; % Input fraction length cic = mfilt.cicdecim(r,m,n); cic.InputFracLength = IFL; I use fvtool to check the impusle response and I got figure 1 attached , 9330093299 I also use