Search Engine www.edaboard.com

Clock Freq

Add Question

190 Threads found on edaboard.com: Clock Freq
I think you want to find the maximum freq that your design can work at. This will be defined by the longest path of your computational logic. You should first define the clock frequency you have in your board and assign this to the input clk pin. Then define the clock generated from the PLL (if you have one). After you run (...)
Hello there, I have a question regarding crystal oscillators used to clock various MCUs. In general, the higher the signal frequency is, the better PCB enviroment one has to provide for proper operation. Following this, should one always choose the slowest possible crystal to achieve desired MCU clock frequency by using (...)
I use DE1-SoC (Cyclone V) and I use altera OpenCL SDK. This is my acl_quartus_report.txt ALUTs: 7794 Registers: 9,641 Logic utilization: 5,368 / 32,070 ( 17 % ) ( 16 % ) I/O pins: 103 / 457 ( 23 % ) DSP blocks: 0 / 87 ( 0 % ) Memory bits: 348,224 / 4,065,280 ( 9 % ) M10K blocks: 63 / 397 ( 16 % ) Actual clock freq: 135.639999
Hi All, Might increasing the clock frequency replace clock Uncertainty definitions? I understand that increasing the clock frequency doesn't issue new hold violations. But on another hand, the hold violations should not be solved during the logic synthesis (just during layout phase). So, why should we (...)
I'm programming a PIC16F88 using an ext 8mhz oscillator connected to OSCI pin and I'm able to debug and program the chip thru MPLAB v8.9 and Hitech PRO v9.83. So there are no hardware problems in my target board. BUT I'm doing this because I've never been able to debug it using it's internal clock programmed at the same freq. (8mhz) Everythin
Hi, I am looking for and oscilloscope that would help me to measure these signals: - SPI of at least 20 MHz (the max freq would be of 60 MHz but I could test at 20 MHz) - 12 MHz clock signal - i2c Would this help? I am mostly concerned about the fact that it only has 16K as the memory bu
Hi All, As for the Synthesis/STA is the same to define the clock uncertainty or just increase clock freq definition in the same number? Why defining the clock uncertainty is better (I guess it's better)? Thank you!
Hi Experts, Could someone help me in checking the timing analysis for GPMC interface in layout level simulation. Im new to this. The GPMC interface (clock freq - 100MHz) connection is from AM4377 ARM processor to ASIC - NOR flash, asynchronous, non-multiplexed mode. How to start with checking the timing characteristics for the layout. w
Suppose I want to sample low clock freq. (100MHz) signal with a high clock freq. (150MHz). Both siganl are produced at very close freq., only 50MHz difference. Is the nyquist sampling rate valid here? I mean, nyquist speaks about sampling an analog signal to a digital one, so when vice versa, the analog (...)
If I have a clock of frequency F; I need a digital circuit that can generate frequency (M*F)/N; need Not be a programmable one for eg: given a clock of freq, a circuit to generate 2/3*F freq?
Complete confusion about instruction timing. Yes, a classical 8051 performs 1 instruction cycle per 12 clock cycles, resulting in e.g. 1 ?s instruction cycle with a 12 MHz crystal. But a single C code line is translated to many machine instructions, each of it taking one or two cycles. See below how Keil C translates the inner loop of the
hi, i am using ise design suit. when i do behavioral simulation my output is coming with a latency of 9 clockcycle(what ever be the clock frequency) . but in my post route simulation output is coming after 10 clock cycle(100 mhz). so how can i fix this ??? also output is appearing in -ve half cycle when there is no (...)
The is Impulse noise which has the same spectrum as White Noise but Pink Noise is acoustically preferred at -3dB per octave or 1/2 pole filtered and Brown Noise is -6dBoctave or 1pole filtered PRSG digital noise depends on maximal sequence length and clock rate otherwise it is fairly short loop in seconds or less but otherwise, same spectrum as
To makeup a meaningful question, you should mention the used hardware (e.g. microcontroller). At first sight 25 MHz clock won't give 50 ns rather than 40 ns delay/pwm step size.
Hii all, i have Input freq. 0,5v to 3,25v Output PWM have 2-256 cycles clock freq. 24MHz. I want to give if Input = 0,5v then Deadtime = 2 & if Input = 0,5v then Deadtime = 24. Is there any equation to do this? Regards Max
thanks ads-ee. I was looking for depth of fifo in asycn clock cases when read freq> write freq. Because the read is happening more often and we want fifo only for synchronization, i think 2 deep fifo should do, " irrespective of the read/write freq value". This is my assumption. I am not sure about this number, so seeking (...)
if TCXO is the clock source, after it goes through the PLL, will it still have same stability? For example, TCXO oscillator is 1ppm & 16MHz, after the PLL, the freq becomes 48Mhz, will the 48MHZ clock still maintain 1ppm stability?
Explain how the system has to work in detail. Mention MCU you will use, clock freq etc...
1553 modulation is Biphase , so clock recovery to 0.1% long term is normal, short term depends on Noise and method used, PLL or 1-shot at 3/4T i have no idea why they specify freq error on Biphase , when for Rx, only phase noise and phase margin counts.
Hello everyone, I'm looking for a PLL IC which will take an input of a 10Mhz square wave pulse from a signal generator and will produce a 500Mhz square wave pulse at the output. I'm getting lost with all the PLL's out there. Can someone please suggest a good IC that will perform the task at hand? Thanks, Funkymix89