Search Engine www.edaboard.com

Clock Gate Timing

Add Question

47 Threads found on edaboard.com: Clock Gate Timing
it is not a good idea to implement a clock gater cell because of timing issues with gates put in the clock gate. as far as I have seen...most library vendors will provide a set of clock gaters(I have yet to see a library with clock (...)
Hi, considering RTL code as below, at time=100(ns), A is forced to 1'b1. a) In RTL (zero-delay-mode) simulation, I am able to see A2 becomes 1'b1 at positive clock edge at 100ns. b) however, in gate level (post-synthesis) (zero-delay-mode) simulation, I am not able to see A2 becomes 1'b1 at positive clock edge at 100ns. Anyone may help (...)
Hi all, I have two questions : 1). We know about the time borrowing from a latch, so is the borrowing inferred during timing analysis by the tool or inference comes from a lib? 2). Similarly we know that a clock gating cell is made up of a latch and an combo gate, so can time be borrowed from the ICG as well? Thanks in advance (...)
I am building a digital clock timer using 74192 and 7447 decoder. Hertz is 1 (1 sec) clock. On proteus, on the tenth of seconds, i trapped the #2 and #4 bit which equals to 6 with AND gate then connected to reset of the 74192 so when it reached 60 secs, it will reset, but what happens was after 39 secs, which should be 40 secs, it resets (...)
If we do not define clock, than what happened? Synthesis failed means shows the error/message or it just create the RTL to gate Level netlist? -> RTL -> gates conversion doesn't need clock definition. -> you can use any other constraints to define the timing for your design(like max delays etc). -> (...)
Here is a very basic concept idea without using a micro (may be easier though), based on a stable clock for setting the time that the input signal must be above the required threshold. The comparator opens the counting gate to (U2: 4017). It also set the logic to enable (U5: 4013) to be set by the output from the counter. The specific cou
Maybe because of clock (timing) recovery technique like e.g. early-late gate on packet preamble?
Hi friends I want to know how can i SDF annotate only clock domain crossings (CDC) in a gate-level netlist during gate-level "timing" simulation? SDF file contains all the gate and interconnect delays of cells in a synthesized netlist. How to make sure that i do SDF back-annotation of only CDC paths and (...)
Apart from the problem, that the asynchronous reset may cause a timing violation (e.g. being too short), some artefacts in the simulation waveforms suggests a serious hardware problem, e.g. the reset spike occuring on the first clock edge. In so far, post #2 seems to hit the point.
The generation of enable to the clock gating. The register which generates the clock enable is also expanded in clock tree synthesis then timing closure of clock gating enable on root clock would be very tough. So bottom line is we should not expand the clock tree on (...)
Hi, I am trying to do functional gate-level simulation (zero-delay) which means withOUT timing. Please see the attached figure When i run the gate-level simulation of the original design, it takes 160 minutes of wall clock time. When i partition the design into 2 partitions and do mixed RTL and (...)
Hi guys, sorry for may be asking a simple question. We know that for "Registers" in a design, the timing difference between RTL and gate-level (timing) simulation cannot exceed the clock period minus the setup time because else there would be a setup time violation. Now can we say the same thing about combinational (...)
Is this clock generated out from the CLKGEN ckt?. From your description, there is control logic to generate the clock to your ckt. Follow these steps to find the root cause ?. I assume tool used for signoff is synopsys. Ask your timing engineer to trace the fanin of the clock. (report_transisitve_fanin -to
Someone said that the SDF gate simulation will check the false path is correctly setting in the timing constraint(.pt). But I think it's not reasonable because in the test bench, the clock generation is different with the clock setting(synchronous or asynchronous) in the timing constraint. So the (...)
hai everyone , we see setup , hold clock gate , io-flop , flop-io and io-io etc violations and issues in timing analysis . can anyone provide me any material regarding what must be done and observed during power analysis. what are the different issues.any document will help a lot. i use apache and pt tool for ir drop analysis.
hi, when there is positive edge clock and change in input cause the output to one... wat may be the circuit for this condition?????????
In our project we have a PLL which outputs two clocks and they are XOR-ed to generate a clock with 2x higher frequency. When we do STA, we have problem because when creating generated clocks doubling clock isn't supported, so we can't get the delay from PLL and through the XOR gate (...)
Hi, Friends: I meet a problem when using synopsys power compiler to do Latch based clock gating. I want aviod cross clock domain data, multi-cycle path data and data from chip input port been used to do clock gating enable calculation. While power compiler do use these signal to do clock gating enable (...)
Hi friends, I wants to phase shift the clock which is used in the process, means the clock is used in the sensitivity list. For example, my clock is 200 Mhz, so i wants to generate a clock with same frequency but different phase (say, 90 or 45 degree). the thing we have to noted is that the same clock is (...)
yes ,it is timing simulation. and functional analysis is right ,but gate-level simulation has problem So it's simple now. You just need make your clock run slowly. Such as 1MHZ. HaHa.