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40 Threads found on Clock Phase Shift
One option is to use a phase shifted version of the clock coming from a DCM. A second option is to use the IODELAY2 to phase shift all the data outputs by more than the 1 ns. See I/O Delay Overview starting at page 70 in the Spartan-6 FPGA SelectIO Resources doc
There are many unclear points in this thread, e.g. what's the purpose of 3 data clocks. A timing diagram would surely help to understand the problem. I agree with KlausST that a single data rate signal with accompanying clock can be read in without a PLL. In some cases a PLL can be helpful though, e.g. to generate a sample clock with (...)
I had a thought - that is usually dangerous so read on with caution: I have to design a low cost radio time code receiver for use in the UK. It isn't a "wall clock", it has to format the date and time so it fits in a packetized data stream but I can do that easily. There are two radio references I can use, an ASK signal on 60KHz (similar to DCF77
Hi all I am investigating the response of a circuit in which two synchronous clocks with 180 phase shift are connected by two 10 kohm resistors and the output is the common signal between the two resistors. May anybody help please?
Let's see if I can help. I'm assuming the issues are with the -/+ values used in the timing report? - Setup xxxx destination setup time means that we remove that time from the period, as the signal needs to arrive that much earlier than the clock edge at the destination. + phase shift xxxx How should i interpret this pha
I don't even understand what's 90 degree for a two-phase clock. I would expect 0 and 180 degree nominal phases. At least some explanation needed. How do you analyze the circuit? Which tool reports the said 93 degree pahse? Generally speaking, it's a property of your clock generation circuit, not the SC filter itself.
The most accurate way is to use an accurate clock that runs much faster and count the time interval. If counting is not possible, a DAC could be connected to counter to read as Analog. The Type I is just an XOR Gate mixer so with steady frequency and Vcc, the average phase voltage can be measured for 90 deg +/-90deg shift which can be a (...)
Draw the circuit diagram of a one-bit Dynamic shift Register, based on CMOS inverters and transmission gates, using a 2-phase, non-overlapping clock. Briefly explain the operation of the circuit Modify your design such that it has a parallel input and can store data when the clock is stopped. Briefly explain its (...)
Hi, My design requires two clocks. One clock which has a 90 degree phase shift with respect to the other (but with same frequency). During synthesis (with cadence RC) I defined the first clock as follows: create_clock -name clk1 -period 1000 clk Now how do i specify the (...)
I assume you are generating the 60Hz signal digitally using a 100KHz clock, right? If I understand that correctly, then one way of doing this would be to have a divide-by-1667 counter to generate a 60Hz output. Then, you would have a second "delay" counter that would count a programmable number of clocks before enabling the first counter.
Hi guys So here I am trying to reconstruct a lets say 1MHz square signal using a 50MHz clock signal using Spartan3AN. I know this is absurd but this is actually a part of a bigger problem that I have narrowed down to this simple circuit. So using this 50MHz clock and a series of counters I get a perfect result. a clean 1MHz output mimicking the in
I have removal check violation during timing analysis. When I looked at the report, the asynchronous reset goes to two flops, one is clocked by the clock twice faster than the other one. The two clocks are synchronous(same phase). While calculating removal check for slower clock, it is adding one (...)
Hi, I'm trying to connect multiple 74hc595 shift register in series so that I can get more than 8 bits output. The problem is that the data output of the first shift register, which is supposed to be the data input to the second sr, is early by half of a clock cycle relative to the input data. The attached scope picture shows what I mean. (...)
how to implement clock multiplication by 2 in digital phase shifting the clock by 90 degree and xor results in multiply by 2.. if this is the answer how to do phase shift thanks in advance
Hello, imbichie, Thanks for your reply. I am a rookie in DCM. So please correct my design. Here, in Xilinx DCM, a phase shift resolution 256 of the CLKIN's clock period can be achieved. in my design, the higher phaseshift resolution the better. If I use a f/2 directly from 6MHz to get the 3MHz (...)
Hi, I am trying to design a clock recovery ckt for a serial input data. I came accross many materials which implement phase Frequency detectors using the RS Flip Flop However I am unable to resolve the fact that it needs a reference clock signal in addition to the existing VCO clk. My requirement is as follows :- -> I get a random (...)
Hi I need to two clock(LO) for I, Q from one clock source (same freq. or higher) they must have same precise phase-difference(90 degree) anytime. how could i get? plz give me the keyword to search.
Hi, I had a doubt on DCM in FPGA Xilinix Virtex-4 , the phase shift part (Digital phase shift) DPS....can you explain clearly...plz help in this ...waitng 4 ur reply....
hi all, is there any relation between trace length and phase of a clock signal ? i have to two clock signals of same frequency coming to two devices that should be same in trace length but if there is some difference between the traces then what will be phase difference between the two?
If the signal to be shifted has a period of 4x multiple of the clock, you can use a counter to make it 90 degree shift. But exact 90 degree isn't possible.