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Clock Tree Simulation

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10 Threads found on edaboard.com: Clock Tree Simulation
Hi all, I'm using Design Compiler for synthesis my verilog code. When I synthesis my code without clock-gating, there is no timing violation in synthesis report and post-synthesis simulation with VCS. And then I re-synthesis with -gate_clock option to compile_ultra commands and the synthesis report says no timing violation occurs. (...)
Hi all I have gatenetlist for postsim and SDF. This files are produced from post simulation. Of course, scan and clock tree synthesis was did. I'm going to apply this postsim gatenetlist to xilinx ISE with SDF for make FPGA bit file. That is, i want to apply FPGA to netlist included delay information. But i cant now know (...)
I have question about how to simulation a clock tree using HSPICE or Nanosim for power and noise information on clock tree. The procedure I am thinking is to extract clock tree from the design and then simulate. How can I extract clock (...)
Pre-layout simulation is the one you use to check if your gate-level netlist (right after Synthesis) is functionally correct.but the post layout simulation "no longer in use" was to check that the gate-level netlist is still functionally equivalent the pre-layout one because you have added the clock tree, buffers,scan chains et
i am trying to do a simulation with a pre-CTS sdf, so i am forced to hack the clock tree cell delay and interconnect delay to 0, but it will cause hold timing violation on DFF, so, how can i turn off "hold" timing check in ncverilog? i know, i can make sdf annotator ignore hold time annotation, but the verilog library still has that specify...
Hi, Im doing gate level timing simulation. Im getting in glitch in PLL clock out, which translates as X (during glitch period), when it passes through clock tree buffers, this clk with glitch goes to CLK Divider flop ( no timing chk is added to clk divider flops), but still Flop output is giving X as result of glitch. (...)
clock skew is a major problem in the design of large-scale high-speed ASICs. CTS layouts that use a dedicated clock trunk line or CTS to resolve this clock skew problem. Through buffer insertion and layout and flip-flop layout is performed to minimize clock skew in the chip.
Using any backend flow is going to take a long long time. Not practical. Using any RTL power estimation is way off reality. Using gatelevel simulation (after P&R gate, so the clock tree is there). Basically, the flow is: you prepare the gatelevel netlist, get SDF from backend people as well as parasitic information (the cap and (...)
hi all! I am sure the sdf file has been annotated to post layout netlist! but in wave trace,I can't see the delay. For example, the clock propagated throgh the clock tree. thanks a lot!
Hi, Does anyone know how to do the spice simulation for the clock tree and for timing analysis? This is a digital design and want to do spice simulation for clock tree, timing analysis and noise analysis. what are the commands for this in hspice and how to look for in the result, i mean (...)