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18 Threads found on edaboard.com: Cmos Charge Pump Design
Hello, I need to design a cmos based gate driver circuit for buck dc-dc converter. A bootstrap capacitor based architecture is needed . Does anyone know useful papers or documents for this ? Thanks..........
Cap values were entered incorrect.. Always Double check.. uF not F Op Amps are not intended to drive inductive boost regulators. For this we use cmos diode voltage doubler strings with charge pump boost design. See same name in IC's
charge pump circuit is designed on 180nm cmos technology. and width of UP, DN pulse is 100ps (In CDR circuit 5Gb/s(1UI=200ps), lock condition UP=0.5UI DN:0.5UI (full rate hogge PD)) is it impossible on 180nm technology(speed limitation)??? Maybe the frequency at which you are switching the pink color current is clo
Look for MESFET designs in cmos, a charge pump can raise 2.5V Vdd to get enhanced performance eg
Hi all, I need help to design a charge pump from 2-2.5 Vin to 3.3 Vout, with a 20mA current load, f=1MHz using a cmos 0.35u process. I do not have particular spec on efficiency. It is possible to use only internal components or I require external capacitor? Do you have a simple but working output voltage control scheme (...)
I couldn't understand the following sentences in Baker's book, "cmos: Circuit design, Layout, and Simulation, 2nd Ed.". p544, 18.4.1 Increasing the Output Voltage "Note that MOSFETs M2 and M3 are not needed, unless the pump drives a DC load, they never turn on. Also, separating points D and E is unnecessary unless the (...)
I've made over 70V in 3V cmos SOI, so it seems plenty possible to me. Depending on the details such as, JI or SOI, junction or gate breakdown at 120V, etc.
hi, all, now i design a DICKSON charge pump with 0.6-um low voltage DPDM cmos process, input dc voltage is +3V, and i hope the output is -3V. but the output voltage is only about -1.2V. why? Need your helps! best regards,
Hi,every one : I am designing a charge pump pll. I found the bias current ckt and low pass filter need resistors , but the process (soi cmos) I use don't provide resistor device. So my questions are : How to design the bias and filter ckt without resistgor? Wheather may I use mos fet woking as (...)
hi : I want design a charge pump pll. But the process (SOI cmos) does't provide resistor device. So , any one can give suggestion on the design of resistor-less filter and bias ckt of cp pll ?
Hi All i want to design negative chrage pump in cmos design kit i can't find circuits for negative charge pump can you help me ? Best Regards
Hello. I need to design a substrate charge pump to generate a negative substrate bias. The picture shows a simple substrate pump basic cell proposed in the Baker Li "cmos Circuit design, Layout and anyone tell me any formulas to design this circuit
For low efficiency application , you can refer to page 366~369 of <cmos circuit design layout and simulation> by R.Jocob Baker Harry David E.Boyce.
For your application, you can also refer to: A -90-dB THD rail-to-rail input opamp using a new local charge pump in cmos Duisters, T.A.F.; Dijkmans, E.C.; Solid-State Circuits, IEEE Journal of Volume 33, Issue 7, July 1998 Page(s):947 - 955
There are already many cmos process which can support HV for at least 12V as Flash macro needs 12.5V for charge pump, so you may not need LDMOS. Sorry that I don't know LDMOS. Cannot give further help. If u need help on LDO design, we can share instead
Can somebody give me papers/reports on design of High Current(>50mA) charge pump Voltage doublers using cmos? I have tried looking on the web but all I can find is PLL charge pumps which use very little current. I need one for very large current? Thanks Suhas
hi just wondering... how can i generate negative voltage in cmos... lets say my vdd is 3.3 v and i need to generate a negative voltage lets say -2.5 volt. how would i do it? ?
Hi guys Anybody has good reference docs which describes common used charge pump architectures in cmos? Thanks in advance Greetz Joris