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44 Threads found on edaboard.com: Cmos Regulator
CD4000 cmos logic is working over 3 to 15 V supply voltage range. There's however no logic IC family designed for 24 V supply.
PMOS LDOs always have a hard time with HF PSRR, any groundward jerk on the pass FET gate is directly amplified (common source amplifier). In normal cmos techologies ground parasitics are pervasive. You may need to look at compensation schemes (like, Miller makes it worse as any drain jerk - which would include + supply movement, relative to the f
Hi, The following pic shows cmos current to voltage converter (for DC-DC converters application),can any one help me to know the design steps and suitable opamp required?
By literature studies
Hello, Do you believe that the MCP1703 (sot89) 5v regulator can deliver 5V to a circuit which is pulling zero amps through it? (not loading it at all?) Figure 5 of the datasheet (fig 2-3) appears to suggest so. Its just that im using it to supply a few cmos chips and wonder if at start up, before much load current is being pulled, maybe the o
I need cmos implementation on TSMC90 nm technology for example.
Though i did not design the LDO for your specs..but the structure on cmos may look something like shown in figures attached. I used folded cascode opamp for error amplifier with output stage W/L chosen for 10mA output current. My supply voltage varies from 3.2V to 4.2V. obrazki
Hi, At present, I am learning about Switched-mode power supply and Low drop out regulator using cmos. Could anyone suggest some good books about this? The main problem here is "using cmos". Thanks.
Any good book or resource which discusses voltage regulator design in cmos technology
Hello, I would like to know the layout issues for a low dropout regulator (LDO) in cmos technology. Can you name a document which shows a schematic and the associated layout issues ( like minimizing parasitics and track resistance etc..) for the LDO ?? Thanks in advance.
Hi All, could please someone recommend me a book or a document with a compilation of basic analog building blocks in cmos, like for example: power on reset undervoltage detection voltage regulator 0scillator bias generator bandgap etc what I am looking for is not a theory book but a compilation of different topologies, if possible
A Low-Voltage, Low Quiescent Current, Low Drop-Out regulator,AN AREA-EFFICIENT cmos BAND-GAP REFERENCE CIRCUIT FOR LOW SUPPLY VOLTAGES,,,A Low Power VLSI Implementation for JPEG2000 Codec
I agree, that the unregulated DC/DC converter can be a problem, particularly because the sensitivity of the GM tube depends on the HV level. The logic ICs are standard cmos, I guess, and can manage an even higher supply level. A LDO regulator, e.g. LP2985-5.0 or -5.3 should do the job. It has only a low mV dropout voltage and a moderate current
Hello All, I want to design 12V-5V Unregulated I/P to 3.3V,1A Regulated O/P Linear Voltage regulator using cmos 0.6um Technology with Cadence tool. Can any one please suggest me correct Topology? I have knowledge of LDO but I am not sure for this problem LDO topogoly is suitable or what because Drop out voltage range is very big. Any re
Hi, I want this paper, could you help me if you have? Thanks for your kindly help in advance 1. A Low Noise cmos Low Dropout regulator with an Area-Efficient Bandgap Reference SUMMARY In a low dropout (LDO) linear regulator whose reference voltage is supplied by a bandgap reference, double stacked diodes increase the effective (...)
Dear cmos: it is not that simple. The voltage regulator canīt sink current, only source. When the relays are switched off the free whell diodes carry their current directly to the power supply, but it canīt sink this current. This means a voltage spike will happen that can affect the mcu operation. Regards
Hi to all ASM masters. Basically i am doing a project on wattmeter using PIC, LCD and other components like cmos voltage converter, 3.3V regulator etc. But when it comes to ASM, i headache. To be honest I am getting the asm source code from the web (here), and the latest is that the digital IO on RB6 and RB7 is enabled. However when I go through
A 9.953-12.5GHz 0.13μm standard cmos bondwire LC oscillator using a resistor-tuned varactor and a low-noise dual-regulator Maxim, A.; Turinici, C. Radio Frequency Integrated Circuits (RFIC) Symposium, 2006 IEEE Volume , Issue , 11-13 June 2006 Page(s):4 pp. - 344 Digital Object Identifier 10.1109/RFIC.2006.1651161 Summary:Notice of Viol
In .18 process,there are some kinds of mosfet,for example,mos in 3.3V ,mos in 1.8V,can I use them in one circuit.thanks!
Hi, I need some reference voltages for a CIS chip. These references will also go off-chip, but has to be generated on-chip. Some of them are between the rails, but some aren't. The supplies are 0V for gnd and 3.3V for vdd. Transistors can work up to 6V. I need to generate a couple of references a little bit below 3.3V (say 2.7V) I need to g