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20 Threads found on Comparator Region
what is the linear region and slew rate limited region in comparators?
the sense amplifier is a regenerative circuit. It is as if you're asking whether a clocked comparator operates in triode or saturation.
This application is using FET as a switch, which is most common use of FET. In mcu when you set reference voltage for a comparator,it is same type of application. Detail of this module can be seen in datasheets. Digital ics use FETs for logic level switching. Fet can also be driven in analoge region. It is used as variable resistor in feedback co
LM3915 is the most popular LED bargraph driver, so if it's not available in your region, I fear that it's unlikely to find a replacement. The best solution is most likely to create a similar functionality from standard IC, e.g. 3 LM339 4x comparator and an OP for the input amplifier/rectifier, also resistors as LED current limiters and a reference
Hi Does anyone know about comparator design challenges in subthreshold region? Tx
hi,there i have designed a comparator and the pre-amp is given in pic1.The top mos pair is working in triode region when the CLK signal is low and act as resistors.And the mos pair below the resistors are just switch to perform the dynamic compare. Recently I found there are some problems in my pre-amp. In the pic2,I found that the (...)
Hello All, I have some questions about cmos comparator design. I need to design a very low power comparator. The Vdd = 3.3V, Midband Gain ~55dB, GBW ~500KHz. The current needs to be as small as possible. I plan to put the differential pair in subthreshold region and the rest of the transistors in strong inversion or moderate (...)
i heard that if we use of open loop opamp as a comparator, it's not needed to use of input common mode for opamp inputs(without dc biasing) and only apply Vin & Vref. is it true? i think that if we need specific resolution, we must have specific gain.if we don't use of Vcmi, transistors will not be in saturation regime, thus we have not desired g
Hi, There are some doubts:- (1) Is the output of inverter connected to B_0 as input? (2)What will happen if both A_0 and B_0 go high? (3) Is this purely as comparator? (4) The input to xtors wont be varying much, so that the current can always be flowi8ng through them, am i right? Thank u
It's a fig of operation reagion of comparator. And the formula describes the vout when the comparator work in the REG_MIN region (which is a Linear region). My question is : 1. How could we derive the formula? I think
What's the relationship between comparator's resolution and offset voltage? :|
I think the m1 and m1 must be in saturate region.then comparator works correctly
Is every MOS device of hysterisis comparator in saturation region? I think some devices are in triode region. Am I right?
for a comparator, if the input voltage is changed from low to high or from high to low, some transistors must change their operation state such as from saturation to linear to shut-off. in my opinion, for hysterisis comparator, some transistors will operate in shut region in turn.
Hi, To your first question....if your reference voltage is VDD then your comparator design would be very difficult because when the input voltage of comparator is Vdd , preamps go into linear region while the other input is sitting at Vdd/2. Instead a simpler solution would be to use some technique to scale the input to ADC by a fraction (...)
If the two differential input transistors of comparator work in subthreshold region due to low current, is there any negative effect or anything should be careful during design?
Linearity is important for Op-Amps while comparators do not care about the distortion of outputs.
everything in saturation? no, it is not right. Maneatis load should not be all in satiration region. U may not understand maneatis load's theory. u need a buffer first to increas the vco swing and then followed a comparator. buffer can have the same structure as ur vco cell. hi actually i used the maneatis delay cell ins
Can anybody suggest some low voltage 1.3V If the conventional differential amplifier is used as a comparator, then the diode drop of the upper diode connected pmos transistor ( in the current mirror) puts the input nmos into triode region.
I have designed a comparator. The output stage is made up of a pmos and nmos transistors (just like in an opamp output stage). The nmos is in triode region and I believe that is how it should be when the pmos is in saturation. Just wanted to know if anyone thinks if both of them should be in saturation. Thanks

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