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24 Threads found on Comparator Vhdl
Are you trying to build a clocked comparator? This pseudo code might help you. process(clock, rst, ip_signals, op_signals) begin if (rst = '1') then -- Initialise the comp o/p signal (Set/Reset the comparator) else if (clock='1' and clock'event) then -- Give your comparision condit
The vhdl code will surely generate an 1% duty cycle pulse (not a legal servo pulse width, I presume) with fclk/1000001. In case of a 50 MHz clock, a 200 ?s pulse with about 50 Hz repetition. By using an unregistered comparator, the output will have some glitches, you may want to correct it. No idea how you managed to get no output in your te
it will be a mux on the counter register. The comparator provides the select for the mux.
can anyone pls help me how to design a double tail comparator in vhdl using modelsim software......actually im feeling very difficult in designing a each and every transistor in that double tail comparator circuit....
can anyone pls help me to design double tail comparator in vhdl ?...
hi all, i got a vhdl assignment and im stuck. i need to create a controller and data path that have 4 numbers as inputs (as well as clk and reset) and i need to arrange them from the smallest to the largest (4 outputs). i also have 1 comparator that i can use as component inside the data path (i can use only one). the comparator have 2 (...)
Hello, i want to make a structual description of a 4bit comparator using GENERATE stratements. my code is this: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY temp1 IS port(Ain,Bin : in std_logic_vector(4 downto 0); PrevA,PrevB: in std_logic; AgB, AlB: out std_logic); END ENTITY temp1; --
Dear all , I am trying to build a comparator in vhdl for a 5-port router north port ,south , east ,west and local port to processing unit I will have an input of 4 bits and these 4 bits will be compared with some x,y coordinates stored for each router's comparator. So lets say that the coordinates are x=1 and y=2 . The coordinates (...)
I will not write all the code for you, just a small snippet but from my understand it seems like you are trying to divide a clock using a counter. This would work as follows: If you want to divide the clock by four for example you would use a signal that could count to 4 and use a comparator to drive an output clock. process( clk ) begin if r
Hi, I am developing an analog FM demodulator in a FPGA. I am trying to implement a limiter. Do you have some suggestion? I tried to implement a hysteresis comparator but the problem is the freqeuncy shfting between the sampling frequency and the incoming frequency... Thanks in advance Best regards. MWMM
Hi, i have to design a parallel LDPC decoder with stochastic decoding capability. The principle is to convert the channel LLR values into stochastic bit stream, where the probability of 1s in the output bit stream is equal to input LLR value. So far i know that to do so, we need a comparator which compares a normally distributed random number R w
I do modeling a wien bridge oscillator and a comparator with hysteresis using vhdlAMS code. please help me
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity comparator is port( a, b, c : in std_logic_vector( 6 downto 0); -- p, D : out std_logic_vector( 3 downto 0)); end comparator; architecture processing of comparator is begin process (a, b, c) begin if (a <= b) then p<="0001"
Can you elaborate on the design requirements? Is this part of a feedback loop? If so, what are the specs of the ADC? How many bits of data are being compared? The more info you can provide, the better the recommendations. 8-bit unsigned comparator: -- Unsigned 8-bit greater or equal comparator. library ieee;
Dear every body I want to know how I can optimize space used of cpld or fpga based on vhdl code to reduce consumed space. I think most of used space for my code (chich is unnormal) is due to presence of one 24 bits comparator: if (ASig < 8e6) then ....... end if;
Hi guys, I am designing a circuit that will convert 12V signal into digital through a comparator and that needs to be read by FPGA. (1) If I don't use a common GND for the comparator and the FPGA, do I have to use Differantial inputs? (2) Which IO Standard do I use, and where can I get their specifications (3) Can someone advise me o
Hi guys, I want to feed 4 signals to a MUX (run on FPGA supplied clock), and then to a comparator, which feeds the 4 bits in series to an FPGA input. Will this work? Can anyone advise me on how to go about making verilog or vhdl code for reading serial data - either SPI or otherwise. Also, i need advice on synchronization techniq
Hi, Try to remove lengthy that, its better to debug the code...but any how check out these lines ??? I see that nwe as well as addr are not assigned with any it true?? -- If the comparator is in rec_data state and input data is valid, then -- the sram write enable is asserted so that the IV data can be stored
Here it goes ... Hope this helps! library ieee; use ieee.std_logic_1164.all; entity comparator is port ( A : in std_logic_vector(1 downto 0); B : in std_logic_vector(1 downto 0); L_in : in std_logic; G_in : in std_logic; E_in : in std_logic; L : out std_logic; G : out std_logic; E : out