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5 Threads found on Compile Edif
First of all - YOUR POST IS ABOUT DIGITAL, not ANALOG. Get your posting right and don't cross-post. Now let me think. I did this once but I used Symplicity to compile to gates and output edif. Then, import edif into the LED SPR and run using a tdb file of standard cells. But you are right - getting a SYN file for your TDB is the (...)
Don't know if this works for you or not: current_design block_A ... contraint for A ... current_design block_B ... contraint for B ... current_design top ... other constraints ... compile -inc
I was wondering if anyone has any tips in importing edif file from Orcad Capture to xilinx webpack? I cannot seem to get my design to compile in xilinx webpack. Also can I run the simulator with an edif file in xilinx Webpack?
When use @ltera LPM_ROM and @ltera ROM INITIAL FILE to generate LPM_ROM verilog Ccde(With inital value file .HEX) then call synplify to produce .edf file to let altera compile to produce .sof file it show Error: Can't compile edif Input File due to syntax error parse error, expecting `'('' trace the error find edf syntax as follow c
You can export netlist from Orcad Capture to many output netlist (edif, VHDL, VERILOG, ..) See Tools->Create netlists->.. But you may need to fix an output source code to compile it correctly.