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130 Threads found on edaboard.com: Congestion
Hello everyone, How do I solve logic congestion problem in ISIS 7 Professional?
what can I do with this information to reduce congestion in the design ? If your design meets timing constrains - why would you bother with congestion reduction of a specific CLB ?
In my design, suppose I have local congestion in an area where the standard cell utilisation is very low, say only 30%. What could be the reason for it and how can I solve it?
In my design, I am having some congestion after post route stage. What are the different methods I can use to reduce the congestion without going back to the previous stages?
Hi I have a design with 35k and i am starting with 60% utilization and 7 metal layers .I have huge congestion nearly 20 and 5 % in H and V respectively.When i am trying to increase height my utilization is very less.even though my congestion is very less.please help me to fix this issue.
It's not hard for us to predict increased traffic worldwide in internet and mobile communications. Greater congestion of communications airwaves. Greater versatility in interfacing with other devices. Increased security from hackers, thieves, etc. Services which can locate one's lost mobile device.
My confusion is that i think both commands do the same. place_opt : optimizes placement of cells to improve timing, congestion. psynopt : Does incremental optimization of cells to improve timing and congestion. Then what is the difference!!? Is it the way they work? Please help me out on this.
analyze cell displacement during legalization. This could happen , when during placement optimization, EDA tool can meet timing by sizing / adding cells. however during legalization of those cells, EDA tool may not find a nearest legal location to place those cells. This may be due to local cell density /pin density / local congestion. hence these
I want to obtain congestion map after global routing in Encounter. I used to command dumpCongesArea, but i don't know that this command how to work... help me, please... - - - Updated - - - also,does anybody knows command "pdi save_design (0-1) arguments" do?
How does the congestion number helps you to estimate the routing issues?
what is the command in soc encounter to see standard cell utilization and congestion both horizontal and vertical ??
When you perform Scan-Chain reorder, you will improvement in congestion number, this will help you in routing phase.
1. report_qor (synopsys DC) - to see overall statistics of setup WNS/TNS. 2. report_timing - to see setup slack of the defined path. 3. report_power - if power is the important goal. 4. if you did physical synthesis (DC topo) - see congestion report, maybe you will need to change floorplan.
Sometimes because the router can't work out how to do it without creating a violation, because congestion is too high.
Hi Guys, Can anyone please explain what is the purpose of following metal orientation in CMOS layout. It reduces routing congestion, any other purpose? Thanks & Regards, Karthik :razz:
Hello, I solved an exercise regarding the TCP congestion control algorithm and I want your feedback because I have a few questions. The exercise says: Given that MSS(Maximum Segment Size)=2KBytes and the congestion Window at the time of a timeout is CongWin=36KBytes, find CongWin after 5 ACKs. My solution is the following: At the t
is the congestion happening in a single entity or multiple entities? using the logic locks you can force the entities into two (or more) separate regions. but obviously this may hurt timing. Do you also have some aggresive timing specs on the design? lots of async logic, or logic between flops?
To reduce congestion in placement, what are the different things that you do?
how congestion is fixed in placement stage ,,,, while fixing it does timing affect ?? if so,,how it affects ? thnx in advance
Hi, Some topics you can delve in :- 1> CTS (the most important part of PnR) 2> Routing, addition of vias, fat vias, double spacing etc... NDR rules 3> placement issues and issues due to congestion 4> Low power, voltage islands, clock gating (difference between ICG and clock gating introduced by the tool) 5> Floorplanning (This needs more of prac