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SIM900 command runs without any problems on a network with apn, a number of directives not implemented on SIM900 and it is impossible to connect to the network. Of course, if a sim900 previous code was not performed previously on the new rules apply at work without any problems. Because of the large number sim900 I use so I can not change all of ou
The autorouter has done exactly what it is asked to do--connect some points together. It is not designed to read your mind. If you have very specific requirements, there are rules that can help force the autorouter to think like you (for instance, defining differential pairs), but it's not you. That's why if you have a critical path you should r
Hi guys, Normally my friend will use ripup and route to connect those error line after the autorouting for reducing the error after DRC. Is there any easier way than the manual routing? Thanks 107919 Regards, YY
Guys, I tried to do auto routing on altium but the software is freezing, Anyone has a clue why ? I only connect one net and create the edge connector by myself, is it because of my connector ? Please see my screenshot attached, 89994 Thanks
Hi I am drawing the layout of my circuit using Virtuoso. I am using create path command to connect different blocks. By mistake I pressed some key. Now, when I draw a path it shows the DRC rules ( like minimum metal width, minimum spacing) which makes the layout drawing easier. I tried to figure out how I should setup the Virtuoso to do this b
How did you connect the input switches? From pin to gnd or vdd? They should be connected from pin to gnd in your case.
Can you be a little more specific about your project? What are you simulating? If it planar (microstrip for example) the rules for defining size of waveguide port exist (depend on substrate height & microstrip width). Additonally for planar projects i usually simulate SMA connectors to connect to lines (after it i added waveguide port to SMA (...)
... use Via5 to connect ME5 and ME6. Actually, CTM is connected to ME6 by Via5. Though DRC will tell you that these two pins are short, but that's ok. ... and the DRC rules should be aware of this!
Sandhya, A few comments: 1. you seem to have all the tracking on the top now - before you had the ground plane on the bottom 2. you have a surplus track that goes round the whole board but doesn't connect to anything. 3. you now have three ground planes on the top. 4. you have changed the minimum width in the design rules to 26mil. I cannot
I just got this doubt. Do walkie talkies connect with some kind of base station? or Is there a direct connection between the transmitter and the receiver? Thanks in advance.
You will always have floating gate errors till you get to the top level and connect to your IO pins. Just ignore them in lower level cells Jgk
Dear All, When I run DRC and LVS for my design, there is an error: Error while compiling rules file /home/user/amsc35/calibre/c35b4/c35b4c3.rules: Error POLYNET1 on line 1738 of $AMS_DIR/calibre/c35b4/ - the POLYNET operation is obsolete. Please use connect or other alternative or contact Mentor (...)
if you want write a rules for two input single output just Open the FIS Editor by typing fuzzy at the MATLAB prompt and add variable(input & output variables). after that open Edit menu and select rules and create your rules. that's easy save file(.fis) and connect with this in M-file if you want.
No it is not possible to do that.. How will you connect 3 ultrasonic sensors and fuzzy logic needs fast operating speed , atmel 89 series controllers are not enough...........
Thank you ajishgopalr for this video i need more and more explanations Shahabaz, it is not possible to explain here the oscillation principle in detail. *Just some basic rules: The keyword for an oscillatory circuit is "positive feedback". That means, you have to connect an amplification unit (gain A) and a passive
1. Is there a route to the ground plane? In general you must add vias from you component layer grounds with a short track - then the plane layer can connect to the ground net. 2. It sounds like you have been routing with a different set of rules to those set by the DRC. I suggest you edit the DRC rules to suit your PCB manufacturer. 3. (...)
tws&rws434 are RF transmitter and receiver OF 434MHz If i am not wrong....You cannot connect them directly to controller.. you need to use encoder and decoder (HT12E and HT12D) ..... AND MOREOVER.... I DONT THINK YOU HAVE ANY EXPERIENCE IN ANY OF THE FORUM BEFORE... YOU NEED TO FOLLOW SOME rules STRICTLY HERE....... 1. NEVER USE SMS SHORT F
You need to setup a polygon connect style rule to direct connect for vias
Hi, I think the problem lies with in the Polygon. You have not connected the polygon to any connection.. if you really want to have a dead polygon (connected to NO Net). Select the option "Pour over same Net polygons only". this would solve the issue.
When mixing VHDL and Verilog design entities, you have to keep the syntax rules of both languages. Your example is using illegal Verilog syntax in the module instantiation, the problem hasn't to do with VHDL or Verilog module. You simply can't connect a variable of the reg type with a module output port. It has to be a wire.
Wear a good Helmet when you connect Eletrolytics the reverse way.:roll::-D:lol:
Check this error message string in your Assura DRC (or ERC) rules' file. The rule violation generating this error message should give you a hint. I'd suspect that your substrate taps are connected to different nodes, which is not allowed.
How would you connect a decoupling/bypass cap (0.1uF) to a negative voltage rail (-5V), does it still connect to GND? The same rules apply as with the positive voltage rail .. see attached picture .. IanP :D
I would like to know why n+ or p+ is used to connect to the nwell or the substrate.Why not n and p directly. Kapil
I need to synchronizes the clock of my DE2 board(altera) from 27MHz to my ADC (ADS7861 - 500Khz). As i need to verify the ADC, therefore i have been asked to constructed a VHDL code in DE2 board and connect to ADC for testing. According the datasheet of ADC, two inputs need to trigger for 1 clock cycle only, therefore i tried to construct code to m
How to set some through hole via's? Need to connect the top with the bottom layer. To place a via manually, use the shortcut PV (Place>Via). To place a via while routing, just change layers - your default via defined by your design rules will be placed when the track changes layers. To set up the via sizes, follow t
The fanout command will not connect to polygon pours automatically. However, when you pour the polygon, you can specify whether you want the polygon to direct connect, or thermal connect to the polygon. In the Design rules, you can choose the width of the thermal relief spokes, and whether you want four or two spokes. The (...)
Hi, I m vv new to analog layout. How to do this pad frame. Lets consider i have analog core with 5 interface pins. I believe i should use top level metal for this pad frame and connect lower levels using vias. 1. how to fix the size of the pad frame for the process avalb with ncsu(i hve gone thro design rules) 2. step my step exa
The bulk (substrate) connection are shorted, so it is clear that you can put the transistors in the same N-well. Of course, you can place the transistors in separate N-wells, and connect by metal the two n-wells. There is no electrical advantage for this approach. In addition, the disadvantage is the area increase. Layout design rules ask, (...)
I wonder, what rules I must observe if I design low power amplifiers. Some of them 1. Long channels 2. Body connect to source instead substrate (I have double NWELL) 3. Guard rings low power or low noise? I think power is not the key performance in amplifiers. it is
How can I customize the connect rules in the HED?, I know that this can be done when using the ADE environment, I need do this under the HED environment.
Hello everyone, I hope everyone is fine. I'm having a problem in exporting my PCB to spectrra. When I try to open the DSN file in spectrra, it flashes and quits. What could be wrong??? Thanks in advance Regards
a) look into thr DRC booklet for the Pad and passivation rules. b) ask your fab rep. if you could do it - some fabs will require a vaiwer .... c) Reason why you need the long pad is probably double bond - why don;t you use two pads as is and connect them with metal on the chip?
When you autoroute, and get some failed connections. How can you quickly find out which connections without having to look through the pcb for ratnests? Also what does it mean when it says failed to complete 0 connections, but 2 contentions? Thanks
I had same problem when I studied ams-simulation with ams-designer. I don't know correct solution till, but i did so. 1. Create lib, ex. "amsLib" 2. Create cellviews for e2l and l2e connect modules in the lib ("symbol" and "verilogams" views) 3. Create cellview for connect rules module in the lib ( "verilogams" view). Name it as (...)
If the multiplyer of the model is not operating, the only solution is to connect 8 transistors in parallel, each with multiplier equal to 1...
Hi, I'm one layout engineer and diffusion layer connecting is prohibited in my design now, but since I modify my design based on last edition and need to check out those diffusion used as connect. According to my experience, maybe I may do it by soft-connect check, so I write such rules as below: *INPUT-LAYER (...)
hi, can any industry person tell what layers are this P tap/ N tap consists of and how is it shown connected in layout. as in our diploma we used to create a N tap for p xixtor and would connect it to Vdd, is it same.. also let me know if any one has more to say on this topic.. thanks in advance, Prasad
to connect the two boards, you can use the sound card of the boards and connect them with a simple wire.
Keep portions of wires you might like to cut or connect in topmost metal layer. The points you might want to connect should not be far apart. The spot you prepare for FIB operation should not be densely populated by unrelated wires or devices.
Hi, My layout pass DRC check, but when I try to do parasitic extraction, it give me errors. :cry: here is the error message: 2 Figure Having Multiple Stamped connections. 6 Figure Causing Multiple Stamped connections. The M1_NWELL and NWELL are the cause I guess, but I have no idea how to fix this problem. I have tried many way only to
Hi, I use Modelsim57c at home. The license works quite well when I connect to the net. (license locked on network card) But the problem is: when I move my notebook offline, Modelsim will report that the license can't be found as soon as it starts and quite automatically. (but works ok if it has started already when it was online) Anyone knows if i