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51 Threads found on edaboard.com: Constant Vgs
... I think it would be due to the exponential dependence on threshold voltage in the subthreshold region. Can't you provide constant current to the diode connected transistors? Temperature dependency of Vds=vgs is very low.
Hi. I am trying to build a full bridge SMPS DC-DC converter. Attached are my primary gate drive waveform (Blue waveform) and Primary output Voltage waveform (yellow waveform). 124867 Problem I am facing is that even when the gate voltage is zero, MOSFET is turned on and it turns off only when a -15V is applied across
What I have learnt so far is ID(Drain current) is a function of vgs(when the MOSFET is operating in active region). Is there any way to maintain ID constant by increasing vgs? Thanks
Hi Just give 2 equals nmos minimum sizes (length, width) and assign Va a dc voltage. Sweep Vc from 0 to some dc number and plot Id1, Id2. I expect Id1 is constant since it is in diode connection and Id2 will go from low to high current because you sweep its gate from 0 to some dc number
Hi all: I am designing a OPA and I set the input gm = 10uA/v = upCox*W/L*(vgs-vth)=(2*upCox*W/L*Id)^(1/2), but I found the upCox doesn't a constant value, it changes with W/L or vgs or vds. How to know the upCox value? Thanks for your reply. mpig
hi all , i saw this curve in many books ,I knew in mosfet id=gm(vgs-vth),but when vds is falling , IL=(VIN-VDS)*t/L,IL=ID which should be rising ! so id should be constant or rising? the picture shows me it is constant ,why?:?: 96672
Hey everybody, I am a novice for the sentaurus, I am trying to use it to simulate a silicon-based MOSFET. When I simulate the transfer characteristics of the device with the vgs=1.5V and VDS=0.05V, the drain current turns out to be constant. And I found the outer gate voltage varies from 0 to 1.5V, however, the inner gate voltage varies from 0
M4 is a constant-current source. You've got (9.1V-vgs) across R15, regardless of the drain voltage.
Hi, I am designing an LNA and at the output I have placed a source follower based buffer. This buffer is giving a constant S22 of -15dB from 660MHz onwards. However if I am checking the transient analysis of the buffer, I find that its vgs = 382mV and gm = 3.9mS, vds = 650mV, id = 200uA. Further if I check the drain current voltage waveform o
... I can't find a way to determine the rate of change of Vds with respect to temperature. If you know the vgs vs. temp. dependency for constant drain current Id, it's just a question of the drain load and its possible temperature dependence.
how to calculate channel length modulation constant lambda in cadence gpdk90nm. i calculated it by gds/id and also by pclm parameter( but the values are 1.5488 and 1 which seems to be very large) as compared to 500nm technology which is given in RAJAVI's book. if u have calculated plz tell me.
I want to use two MOSFETS in parallel, with both of their gates being driven by a single output from and LM324. Is there any reason this is not a good idea? If so, is there anyhting i can do to make it work? Schematic
hi all, I am doing the design of constant current LNA independent of the process. Its structure is the common source topology and the drain voltage is fixed to 1 V while gate voltage varies with different process. But the overdrive voltage Vod=vgs-Vth is nearly fixed for all process. In the simulation,I find the MOS drain current still changes
I found on my notes that for an NMOS with increase in Vsb voltage Body Effect increases, Vt also increases. But it is mentioned that with vgs constant id increases which I feel is wrong since id is proportional to (vgs - Vt)2. Hence I think id should decrease. Please show me the ligh
Square law of CMOS: current is a square function of the input voltage I = K (vgs - Vth)? <- Here is the square ;-) Where K is a constant. If input voltage increases linearly, the current increases by square. For simplicity, we can ignore the threshold voltage and rewrite the equation as: I = K (vgs)? If the input signal (...)
There's a "magic point" where the voltage will be constant, you may have to vary the geometry to see it. VT goes down, subthreshold slope goes up, you balance them.
Supposing Vds is constant, Mos will change from linear region to active region as vgs decreases. As result, output resistance rds will increase.
Dear all, In my design, I have a analog block called "IREF-gen" which supplys bais currents for all other analog blocks in my IC; inside this "IREF_gen", we use a start-up; it comes two sorts of start-up for me: one is using p-n MOS diode-connected to gen constant bias for a NMOS; initially, the NMOS' source volatge is 0V and its vgs is higher
... the pMOSFET will get a big gate-source voltage constant current into a gate-source (resp. gate-bulk) resistor.
Your bias current changes with the supply voltage, this explains why you see a bigger variation with power supply. You should bias your active device with a current source to keep the bias current constant.