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35 Threads found on Core Ground
Respected Experts I am a PhD Student in Aerospace Engineering with research on Control Systems. However, I am stuck in an Image Processing task for my PhD Topic. I have to perform Multi-core Graphical Processing Unit (GPU) based "ground Moving Target Indication (GMTI) using Single Channel Syntetic Aperture Radar. The technique which I am allowed
Hi, I'm designing a SMPS as per EN55011 (CISPR-11 Class-A) radiated emission standard. My SMPS Specifications are as follow: 85-265AC , 50Hz universal input, Output1 (5V/1A), Output 2(24V/0.25A) both are floting ground. All my secondary capacitors are low ESR (Su'scon capacitors), RM8 core transformer is designed with shielded winding & fl
Hi, I would like to put a thyristor with (Ipp=500A 2/10 us) for longitudinal protection( Telcordia G1089-core standard) in E1 circuit. I want to know the number of vias in pcb layout design required to be put for the thyristor pad connecting to the ground for this high current. Is one via enough or multiple vias required? Please help. Re
Hi everybody, I'm working on a Multicore project with Leon3. I've configured a design with 2 Leon3-cores (via make xconfig. I want to know how can each core executes his own code c without OS? for example having 2 instanciated cores where the 1st core executes test0.c, the 2nd executes parallel. can (...)
You would probably start off with things that are sort of philosophical in nature. Such as, channel or channel-less routing? What interconnect plane to route power/ground? Contacts in the cell core, or stubbed out? That kind of thing. These constrain the application / construction in Met1 and maybe Met2, at the least. Then you want to figure out
Hi, I have a design with 5 different and totally isolated cores on one chip. Each core has its on vdd_core/io and vss_core/io. I managed to connect the IO and standard cells correctly. When I do CTS or add Tie-H/L cells in encounter, I need to specify that all Tie-H/L pulling up/down cells from a specific (...)
Hi everyone, First of all I want to apologise for my English. I designed my own board with STM32w108. When I'm trying connect with my board via zl30prgv2 using JTAG interfece I have this error "Can't halt the core". I'm using STM32 ST-LINK Utility. I checked all connections, levels of voltages and connections to the ground. Everything seems cor
Hi everyone, i have some doubt in stack-up design,here i mention two stack-up stack-up (a) and stack-up (b) why core is between inner and ground layer in stack-up (a) instand of this if i use prepreg what will happen in this board core is hard material so we need to use the core in center of stack-up right but in the (...)
The internal voltage regulator is used to drop VDD to 2.5V to power the core digital logic of the PIC24F at 2.5V. If you disable the internal voltage regulator, VDD must be about 2.5V. When you use 3.3V VDD, the internal voltage regulator must be enabled and you must connect the capacitor from VCAP to ground. The IO pins will be roughly equal to VD
They are not to the core itself but a screen between the primary and secondary winding. It is to give better screening between each side and helps eliminate capacitive coupling between them. Brian.
30kHz is irrelevant. It's the edges that matter, and starving the logic core (through the package inductances) will sag the supply / ground span. Determine your worst case switching current impulse condition, simulate that within a decent representation of the package, and look at the rail span. If it dips to below where your logic library timing
You need two screened cables. The screen of one goes to ground with it's inner core wired to the pin next to it. The other cable screen goes to D1/C1 with it's inner core wired to the pin next to it. You can use any kind of testmeter probe but you must wire the inner to the core on each cable together AT THE PROBE. These (...)
I think yes because as we add an io/core power pad, we have to also add an io/core ground pad.
Hi, I'm designing mixed signal circuits. digital circuits are synthesized by Design Compiler and P&R is performed by using Astro. In the floorplan stage, i made core area, power/ground ring, horizontal power/ground rail for standard cells. But, after making floorplan, input/output singal pin position is determined randomly. I (...)
Zuzu The first thing you need to do is to determine how many signal layers you need. Then find out how many Power/ground layers you need for your Power distribution and impedance layers. Also find out what core and prepeg thicknesses your pcb fabricator has in stock. ( using non-stock materials will increase the price and delivery time) Also fi
The two stack up only differs on its build core or prepreg build. If your concern is impedance controlled lines. the two stack up will have the same result on line width. But i read somewhere that core build for four layer have better PCB strength (core in the middle) but i'm not sure if this is true. Anyway you can choose any of the two (...)
For antenna radiation simulations patterns and efficiencies, you can use EM-core to simulate them. Infor for download and antenna design can be found at
what would happen that I forgot to add the power/ground strap in my project? the project area 2x2mm,core 1.4x1.4mm, o.13um technology, Because my carelessness, the last layout mistake the strap, NOW , the masks always were made. what would happen? Can the chip run? How to retrieval it? My GOD ! My boss will Kill me! (::::::::::::::
During Ton, the transformer core becomes magnetized and one secondary coil applies a voltage to the filter inductor. What happens during Toff I understand less. I read that half the inductor current flows through each secondary coil. So the input voltage to the inductor must go below ground to forward bias the diodes. Looking at the dot convention
I am designing a mixer to operate at 2.4 GHz.. and have an inductor that has to be grounded in the matching network...since I am using microstrip i know i'll have to drill a hole to connect it to ground spiral inductor the best route to go or an air core inductor which i'll have to wind myself...also when designing a spiral inductor in mom