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Counter Vhdl Delay

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21 Threads found on Counter Vhdl Delay
I see that the counter sometimes misses the rising edge of the CLK signal (please refer the screenshot below, where the counter was not incremented at the rising edge of the CLK signal at 70ns) No, you are simply misunderstanding the logic you created. You build an additional delay of one clock cycle by assigning the output inside t
Hi, I am working on 7 segment display of nexys2 board Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity main is port( clock : in STD_LOGIC; sevenseg : out STD_LOGIC_VECTOR(6 downto 0); anodes : out STD_LOGIC_VECTOR(3 downto 0); switches :
Don't use wait!!!! You need to have a counter or a clock to generate that delay
I have a code simulating a flash memory where it receives a reset signal, and after receiving that signal it starts working only after a particular time "reset time = 200 ns" if before the end of this 200ns the reset signal comes again then the 200ns need to be reconsidered and the "reset counter " needs to be started
First of all, you need a clock input. With a known clock speed, you can use a counter to generate a timer.
I have a counter issue though in my tictactoe project design. I need a counter because the design requirements are to delay 2 seconds after the player makes the first tictactoe move. My problem is the signal twosecwait gets set to '1' after a key is pressed by the player and then the counter will see a key is pressed (...)
I am trying to design a tic tac toe game for a project. I need to detect the players first move and then wait 2 seconds before the machine makes a move. I wanted to make the move by the machine in the same "process statement" after the player makes his move but I can't add in a delay inside the process. Should I use a counter and enable this
Yes Please use counter based on the delay will work
the wait statement is only appropriate for simulation. Otherwise stick the data into a memory and use a counter to wait for 100ms. 100ms is a very long time to wait, you may need a BIG buffer to cope with all the backed up data.
the process is missing n6 from the sensitivity list. But you also have problems because you have created an asynchronous counter. Because it has no time base to go from, when you press the button, it will count as fast as the propogation delay, so will increment by one every couple of nanosecons. This is the main reason it appears random when you p
In the original code instead of using a proper delay to avoid a key being detected many times you have used a condition that only reads the pressed button if it was different from the last key pressed, so every key was only detected once. You have to use some kind of counter (delay) so that the input is not read with the clock rate (which (...)
It is not recommended coding practice to use wait statement for synthesis. use 'event attribute, that too for clock rising edge. If you want to create a delay, then go for counter implementation with enable.
I would like to help you.... but i want to know more about the problem first... 1.what are we supposed to do if signal in goes low before your delay counter has finished the programmed you want to get signal_out high as soon as you get the input high or one clock delay is permissible ..?
Wait statements are not synthesizable. You need counters when the proposed code must be synthesizable. Devas
1. how to use delay in vhdl.....(we r using registers but how its gonna work) For the CIC example, let say ur decimation factor = 32 so you will have a 5 bit counter. When this counter reach 32, you will output an output sample. That mean you will only get 1 output sample for each 32 clock cycle. Which mean you had (...)
hi can any one tel the example of how to write the code for creating delay using counter. can u give a simple example vhdl code
delays are not synthesizeable. The only option is, to set up a counter which delays the signal by a known 'count' the frequency at which counter works, and the count will determine the delay Kr, Avi
That's correct. Use a high-speed clock and a counter. Synthesis tools generally don't support delay statements because an FPGA usually doesn't include any predictable delay elements.
Hi, vhdl is a language for synthesis and simulation. You shoud know what kind of instructions are used for synthesis and what kind of instruction are used for simulation. As the nand_gates said, you can design a counter for generating the delay signal.
Hi, I require some design concepts and techniques involved in vlsi (vhdl/verilog with FPGA ) implementation of digital delay locked loop.Generally digital DLL consists of following components. I.Phase detector II.Digitally controlled delay unit III. Digital controller I am trying to use a Up/Down counter for the digit