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From simulation point of view you can try following tricks may be you have tried few or all of them 1. If you know your design frequency just simulate round the design frequency 2. Relax the mesh conditions as goal at hand is not accurate simulation but to identify problem in simulation 3. Monitor your cpu and ram usage during the simulation though
Let's say i have a parallel static ram that is running at one frequency (8 MHz), and a cpu (in the FPGA) tthat is running at a higher frequency (16MHz). The cpu asserts a read or write signal, the ram gets accessed, sets a done flag for one clock, the cpu sees the flag and deassert the request signal. It (...)
I once tried removing one of two ram chips in my computer. Operation bogged down severely. I believe it was doing a lot of memory bank swapping, to compensate for the smaller ram size. Try a utility called SysInternals Process Explorer. It shows more data than Task Manager. Both of the above tell you what processes are running, how much (...)
I have done histogramming before, but because the 2nd port was connected to a cpu, your method was not an option. The only option for the full pel rate histograms was to use 2x pixel clock on port A and do a read-modify-write operation. But this meant the cpu had easy access to the histograms. For anything (...)
Hello All, My system config is ASUS ROG MAXIMUS VII RANGER, Core i7 4970K, 16GB ram, nvidia gtx 770 2GB, 100W Corsair PSU. Im running win 10 (ver 10.0.10240) and having some blue screen errors. I have uploaded the dump file. The cpu is overheating to 100C, to see the main issue, when i see in cpu-ID it shows the cpu is (...)
I would have wanted to avoid different ships (ram/cpu/dac/adc) to do that You could check for "single-chip-audio-codecs". There are options embedding within a single chip a microcontroller and some peripherals. Anyway, an external storage device ( ram / SDcard / etc... ) is mandatory.
Hello All, May be silly to ask, the latest smartphones uses ARM cortex - A (Application series) SoC's which has cpu, GPU, ram and DSP's on single die like tegra and snapdragon. Are these SoC's Von nummen or Harward architecture? or Some hybrid of them? Thanks Ashutosh
im trying to accelerate the simulation. im using i7-5820k cpu @ 3.3GHz 6 core, 128 ram, Tesla K40c and Quadro K620 (graphics cards). im using time domain solver in CST. i set cpu and Hardware acceleration. i thick/select for multithreading (cpu) up to 48 threads (the max) and i thick/select hardware acceleration to 8 (...)
I want interface ram with pic18f87k22 for store data, more specifically i want declare variable in the address of external ram. After reading bunch of forum i conclude that i have to interface ram parallel, which is supported by this cpu and use extended mode. (See attachment for clarification) I am not able find specific (...)
If you answer the question from the ram chip perspective, there will be e.g. 4 byte-wide ram chips that hold the 32 bit data and get the same row and column address. In so far the data is stored in one address. But the cpu data model usually represents the data as four bytes with consecutive addresses. Consider that the two less signi
Where register variables are stored in microcontroller memory? As i Know that the register variables are stored in cpu register memory, coming to microcontroller, in which memory these variables are going to store?
Hi, What did you choose? I'm looking for a SBC myself, but I want 2+ Gbe (it doesn't matter the interface - PCIe, USB3.0/etc), 1+ GB ram and dual/quad/etc core at 1+ GHz... Preferably to have an open cpu (such as Freescale) where you can find all the datasheets. Thanks,
hi every one i want to use VMWare Workstation 7 for running Linux Suse on it in order to run Cadence. i worked by it correctly in different laptop, but now in sony vaio laptop (model:SVF152A29W), cpu:core i5, ram:8G i can't run it and this error is shown: obrazki.elektroda.
I tried posting this message in the Professional Hardware and Electronics Design section. Got no comments.Though I would try here. I am one of a small group of people that like to build new boards for the 1980?s era S-100 bus. I have a web site ( ) which gives the details. We just finished doing a new 80386 Master/Slave S
Dear Fania, Survey there is no smd component broken when you decided to clean your laptop board. however this event is maybe related to supply circuit controlled by south bridge. Did you disconnect cpu or ram ? if yes then please check them for properly installation. Regards. Davoud.
Intel dg31pr starting normal but when resetting it shows no display error and on debug card it stops at 1130 error code I have already checked ram cpu smps bios update I have also changed the super I/o ic and crystal but no success pls help me. I once again clarify the problem is when I start it display comes but after restarting it goes display of
I have checked that the cpu heats normal but motherboard not give display I have checked by changing Adp chip but no help.
Hi, i'm new here and still new in FPGA design. i hope this is the right place to post. i had tried an example to design a simple cpu from actually i has no problem with the codes, it's compile successfully but i dont know how to implement this code into altera board DE2. i hope someone can hel
Code in assembly is converted to machine code and then programmed in memory, from where it is executed. It is same as computers using cpu, ram, ROM, Data Bus, system clock, i/o ports etc.
I'm new in mc68000. This is a very good cpu. I desing one board and build it. But not work. The cpu steps eight clock cycle and stop with active _HALT signal. Generating rom select and ram select and other selects from a21-a22-a23 and _AS with 74hc138. Generating _DTACK from 74hc138 Yn with 74hc07. Generating _BERR from _E divided by eight (...)