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5 Threads found on edaboard.com: Create Wire Load
How do we create the wire load models? Is it provided by the fab?
PLE is physical layout estimation. It's supposed to be a more accurate timing model used by the synthesizer to create a better quality netlist. It's supposed to be more accurate then zero wire load (ZWL) but not as accurate as actual wire lengths, capacitance back annotated from physical tools.
Hello, I have right angle placed two probes. I can find open, short, load standards but not through standard. Can I manually create a right angle wire that can connect the two probes? Does it affect the calibration accuracy?
Hi, every body: Does anyone know how to create wire load model? what kind of tools can generate? Thanks wllee
Leave this to back-end tool is prefer. Otherwise u can use DC balance_tree . But u have no location and real wire load data. So this may happen to vilatoe some timing issue if u care about it. I found current library from Main foundry could create large fan-out if u just constraint the trasistion time in their default value (said (...)