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I am trying to perform a loopback with an Altera custom Phy set for 8bit-10bit encoding at the speed of 10gbs with a tx_parallel input of bus of 32bits and a tx_datak of 4bits. The transceiver is not successfully interpreting the k word it is being sent along with tx_datak being raised.I am watching the transmition and tx_serial is outputing the
I am trying to get a PA working (using GALI24+ chip) with the recommended circuit given in the datasheet: I have used Cblock, Cbypass of 10nF each, RFC 150uH, Rbias of 47ohm and Vd =9.4V. But I am not getting any positive gain. What could be the problem here? How can I start debugging the circuit?
Hello all i am using Spartan-6 (XC6SLX45TFGG484-3) and choosing the SP605 board or going for a custom board, having an input Ref Frequency of 200MHz, the available highest freq of operation is 83.33MHz for Microblaze. My custom IPs are running on another clock of 48MHz. How can i reconfigure the Clock Generator to increase the freq...OR is (...)
To design "anything" , 1st you define all input and output constraints and environmental range and supply range. Then you define stability, tolerance and start/stop behavior. Then you can compare solutions. Using custom L/W ratio bandgap voltage reference you can choose e. g. 1.5 and Vds max > Vdd. The Beta Multiplier Current Reference Sourc
In the application schematic of a 9W offline LED driver, they use an input filter inductor (L2) which is 4.7mH. Schematic showing L2: BOM showing L2: Why haven't they just used an off-the-shelf, 4.7mH inductor here? Its much cheaper?
Hi Everyone, Design: I have 2 decoder written in Verilog, and a test bench to generate the decoder input and clock. I have imported all the 3 modules separately and created a schematic view and config view. I have also declared global power supply in the design. I have verified the decoder separately for its functionality using ideal voltage
Dear All, How can I use waveview for a schematic that contains only a veriloga symbol and a voltage source in hspice. No .tr0 file is created instead I'm having .valog! Any help is really appreciated.
Hello.. I have certains full custom cells for which I have defined a verilog interface ( just a black box). They have gnd and vdd as input pins. This verilog module is instantiated many times in a higher level verilog module. When i try to generate a flatened gate level netlist using design compiler, the gnd and vdd pins are removed by DC after
I want to design a synchronous counter with 12 states and synchronous reset by connecting the overflow signal ( CT =15 ) directly to load input ( /M2M1 ) so that I can start the counter at a custom state, what I'm thinking of doing right now is just put flip-flops pre-loaded with my predefined start state at the input of the counter so that (...)
You wish to compose a BASIC program that will operate as a custom database manager, engaging in file input/output to a disk drive, as well as interact with one or more users. This is a major undertaking. It must generate arrays which store students' names, and scores. It must write all this data to a file on disk. Most likely it will be a random
hi all, can anyone please help me? I'm trying to add a custom IP to the EDK.Its just a comparison program, i.e., to compare the input with four values stored as four different signals and if the input is similar to any one of the input, then give the output as 00 or 01 or 10 or 11. this is the Vhdl program for that: (...)
Hello, I have made a custom hardware design of a Encryption chip. It works in this manner, it takes data stream from 8bits input then encrypt the data and send out at 8bits output port. Please advice me, how to measure the 'Throughput' parameter of this chip. Thanks. --Kumar
Hello experts, I am making a full custom design of a carry look ahead adder as my lab assignment. For that I need multiple input NAND gates, varying from 2 input to 5 input (at max). The design constraint is to get minimum delay and minimum area. Please recommend ways to reduce the 2 constraints. Thanks in advance. (...)
Hi I'm try to test my full custom AES chip using FPGA (Virtex-5) with ML505 board from Xilinx. I want the FPGA to give the test vector input to the chip and display the output of my chip in LCD. Has anyone ever done like this before and give me some idea how to do it. Thanks
My questions are: 1. why we should extracts sinusoidal signal? Ans. Generally the input test signal we apply is a sinusoidal signal during simulations, hence this custom function is apparently performing this task. 2. If the bitstreams are not ?1, for example, they are 2bits Quantizer. Then the Vref is what , 1 too? Ans. It depends on the quaniti
74HC165 will do the parallel load aka input and serial the output. you could put the serial output into a 74HC164 to return you a shifted parallel output (shift is displaced by 8bits on each clock,ie the output is 8bits behind) I think that the best you could do without custom wiring up JK flip/flops
I scored a 7-seg LED board from a school basketball court. The unit has four of these massive 13" 7-seg displays with each segment comprising of 15 LED's and is just begging to be turned into a massive clock! I took out the driver boards and they seem to be very simple except their is a custom SOIC chip that I need help figuring out how to opera
That is incorrect - Pspice can be used for 90nm CMOS design or any other IC design. Keith Thanks for your input Keith. But isn't that short of custom design testing done on Hspice? Please educate me how this can be done on Psipce, and where do we find simulation model?
Hi, I need to design a microwave filter in ADS momentum and its shape is custom. Built-in shapes like Mcorn, Mcurve, MTee don't help. For example how can I create hexagonal resonator? Dimensions are important so draw polygon function doesn't help. Any help is appreciated. Thanks.
hello all, I am using virtex 5SX35T custom board in which i want to use microblaze for UART communication and protocol. even if i am writing simple is not seen in hyperterminal... here is the code: #include "xparameters.h" #include "stdio.h" #include "xutil.h" int main (void) { // int input; while(1) { xil_print