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19 Threads found on edaboard.com: Dac Glitch
It would be reasonable to add a few words of specification and analysis, e.g.: - specification of your dac (speed, resolution, supply voltage, output signal level) - what's the observed glitch level - how does it compare with industry standard dacs - can you locate the main cause of glitches
glitch area is only applicable for dac not ADC. glitch is calculated by area of triangle (in OUTPUT Signal) in the analog signal not in Digital signal. Am i right?.
1. You may be able to tailor the capacitor value to be small enough, so that the time constant is so short that the analog output settles quickly, before the next digital value comes along. 2. There are a few methods of dac. You might get better sync if you use a different method. Or perhaps a different binary switching circuit.
I have a montonicity issue with my dac with worst case DNL during transition from 0111 1111 to 1000 000. There is a massive glitch during this transition. the output impedance of current source I designed is very high 10Mohms. I have noticed the glitches in certain bits from the D flip flop outputs which inputs the signal to the switches of (...)
Hi all , I am using a 16 bit R-2R ladder dac for generating voltage output. The analog supply to the dac is ( Avdd/Avss ) +/- 15V and i have configured the dac so as to get output of 10V . When i switch off the analog supply to the dac , the dac output starts decreasing as expected till supply (...)
I design a kind of dac and I find that due to charge injection of switch to the resistor string , the output of dac have glitch about 10mv-20mv even more .I did not know how to solve this problem,who can help me . thanks
how to reduce glitch in R-2R dac . simulation and circuit are in the pictures. Thanks
Hi dears, In my design, dac's output must be glitch free analog outs but i don't know witch topologies of dac can be glitch free and remained High speed?! glitch freeing methods can down speed of dac? Please send any your suggestions or new methods. Regards.
Hi dears, In my design, dac's output must be glitch free analog outs but i don't know witch topologies of dac can be glitch free and remained High speed?! glitch freeing methods can down speed of dac? Please send any your suggestions or new methods. Regards.
the circuit cell Added after 12 minutes: Added after 11 minutes: I'm design a dac used the classic current steering circuit. But I need a large
pros of thermometer code: 1. no glitch will be happened compared to binary code 2. easy understand 3. Often used in current dac and R-ladder dac cons of thermometer code: 1. bit number is large. (8 selections need 8 bits) 2. need decorder if input is an binary array.
i have a problem with my current steering dac (very high glitch) how can i solve it
There is a 10 Bit 200MHz current steering dac, segmented 6+4 architecture. When a thermometer code open, there will be a big glitch. But it is not a real glitch, it is a distortion that the voltage lower than normal. When the binary code changing, the glitch caused by cortrol signal timing mismatch is very small. I don't (...)
Hi, Please refer to Page no 45 (pdf page # 77) of the following thesis for a very good explanation of glitches in a dac. Bharath
Hi all, I am designing 10 bit 100 MSPS dac.on what basis i have to do segmentation? Theoritically,we can have some tradeoffs on power consumption,INL,DNL,glitch and depending on that we will could be either 6+4 or 7+3.which one to take? are there any calculations for that? plz send me if there are any papers for calculations?
I have a FPGA Xilinx that generate a 20 Mhz clock (sclk) for drive a dac, now when I trasmit serial data (sdata) from controller to dac, dac acquire serial datas on falling edge and on rising edge I observe glitch (I have see on modelsim simulation), the question is : If I receive a glitch on rising (...)
Dear all, I'm design a 8-bit current-steering dac,but,the ouput exist glitch always. How to do reduce current cell output glitch? Thanks a lot.
do ur ideal dac contain CLK & DFFs ? if u do have CLK, then u should adjust it to sample the correct output of ADC .
Hi, If the output is always same it is glitch. Depends on the kind of the dac implemented. brmadhukar