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98 Threads found on edaboard.com: Dac Resistor
Without a series resistor, the dac output would show a strong non-linearity. To reduce the PWM ripple effectively without inacceptable response time, a 2nd or 3rd order butterworth low-pass (using one buffer OP) is preferable. The buffer also allows to reduce the filter capacitor size to < 1 uF and use high quality capacitors.
Let's consider a 1.0V supply current-steering 10-bit dac in 90nm. 1LSB will be approximately as small as 1mV. Now, if the current-steering dac is driving an on-chip resistor, then the voltage across this resistor should change by 1mV when the input code changes by 1LSB. If we consider a PMOS current cell for the (...)
For best fidelity a current dac should be operating into a constant voltage (typ virtual ground). This eliminates output common mode (Early or lambda) effects. A current mirror is likely to be more bias-invariant than a resistor, as far as outut voltage deflection vs current in total, but more nonlinear. If you servoed the output voltage
The ATXmega family have a built-in 12 bits dac. Otherwise use a resistive ladder or PWM output as posted above.
More common to use an op amp to make a virtual ground, and the feedback resistor sets the scale. The only current steering dac I ever worked on, had this resistor on chip and trimmed like the rest. Using a high value resistor is a way to get a voltage output on the cheap. But if the output voltage deflection is (...)
As Erikl said, if you need to trim an analogue voltage use a dac. Other trim techniques involve reading data into a shift register at powerup, the outputs of the shift register control individual nmos transistors that short out certain options, this could be shorting out sub-resistors that make up the complete resistor in the band gap (...)
hi, Iam using the dac (AD5422),the out put of the dac in current(0-20mA,4-20mA) and voltage . what is the voltage i have to provide to the current output of the dac to form the loop
The high speed dac is effected in package ,how to sim and design?
Hello guys . Want to ask what is the use of trasmission gate that always on , and put between lsb resistor string for 10 bit dac ? Please refer to attached pic .
I design a kind of dac and I find that due to charge injection of switch to the resistor string , the output of dac have glitch about 10mv-20mv even more .I did not know how to solve this problem,who can help me . thanks
By FSR you pretty much mean resistor changing its value proportionaly to the applied force. So if you have a current source sending current to the sensor you generate a voltage, Then you can measure the voltage with some dac. All you need is a a voltage reference for dac and you are done. Then you have digital value of the voltage and you (...)
Hi I am trying to make a current reference in 90nm CMOS that gives a stable current, approximately 4nA across a wide temperature range. (-55C - 125C) Does anyone here have any experience with current references that operate in this temperature range? From what I have experienced, it is very difficult to get a stable current across this
Hi all I am designing resistor string dac using 0.35um cmos specifiaction is 8bit , 80ks/sec and MAX 10nF load. I have finished designing resistor string and decoder. Finally I am making output buffer(opamp). I have to consider 2 cases load. my question is As I design the opamp for buffer, Will I
is there any matlab mode for resistor-string type dac? How can we simulate the DNL, INL for it?
I found most lcd driver ICs employ the resistor-string type dac. Why not use other types? like capacitor array, current steering. I think resistor-string consumes lots of chip area, so is there any idea to reduce it while still keep 8-bit resolution.
Dear all, Who can tell me how to choose the mismatch value of the res to design the 7bit dac with 128 res in series? I know that a larger size makes a smaller mismatch, but I don't kown what mismatch value can meet my spec. Could you show me some paper about this? Thanks! B.R.
Hi all, I've designed a 10bit 100M current steering dac. The simulation results using ideal voltage supply is good. But when i add simplified bond wire model(2nH inductor + 0.5Ohm resistor) on the VDD and GND. The output is totally wrong and there is a large oscillition. I add a decoupling capacitor between analog vdd and gnd, there is no obvi
The problem is that most of the "standard" parasitic extraction tools do not guarantee extraction accuracy, they can be easily off by 15-20%. The error can be as high as 100-400% for incorrect extraction setup. Max Never heard of that. Re. incorrect extraction setup: The fab/foundry is res
Found this obscure schem, I think the dac input is the bias control, not too familiar with Good luck
In the architecture of dac ,analog part usually use a bandgap voltage, and then ,transfer the voltage to current,where use a voltage to current circuit. As for the graph below,it uses a op and a external resistor. SO,i want to ask why it directly use the bandgap current? i think it is more convenient to realise. if these v-i structure has some