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28 Threads found on ddr2 Memory Controller
I want to write to a ddr2 RAM from a custom architecture. The RAM has 64bits data width and runs at 400MHz. The custom architecture is interfering with the memory controller by using Avalon-MM interface. The memory controller is set to half-rate mode which means local data width is 256bits and one word on (...)
Please anybody tell me, what will be the "test scenarios for verification of ddr2 controller"..?
hello everybody... while i generated the MIG core and do all steps to check the DDR as mentioned { UG818 (v 13.1) } of ISim Hardware Co-Simulation Tutorial: Interacting with Spartan-6 memory controller and On-Board ddr2 memory and reached page 21 : Run the Simulate Behavioral Model process for the mig_hw_tb (...)
Hello, I'm working on a video-processing project. I've been able to program the FPGA and write to the SPI Flash for automatic booting. Now, I'm trying to exercise myself on accessing the ddr2 128 Mbit RAM on Atlys board (Spartan6-based); which is one of the key-component for the final application (I want to use it as a framebuffer for retrieving
hi dear i want to interface Micron's SDRAM MT48LC4M32B2 with the spartan-6 and want to use the built in memory controller. i am confused about how should DQM0-DQM3 pins be connected to DDR or ddr2 there are LDQS, UDQS nd LDM,UDM pins. can i avail this MCB feature of spartan-6 moreover this SDRAM is being powered by 3.3V ?? can i
Hi, I'm looking for a processor with those feature: - price < $30 - DDR / ddr2 memory controller (64bits prefered), - a DMA engine able to transferts from an external parallel bus (running at 125MHz / 32bits) to the the DDR memory. Do you have any reference in mind ? Thanks, Franck.
Hi, I need to design a ddr2 memory controller for Atlys board with Spartan-6 FPGA. I was wondering if someone could suggest some good learning material to understanding the working of DRAMs and memory controllers. I am not looking for memory controller codes but for (...)
Hello all, I have few questions regarding CAS Latency. For example,if the ddr2 SDRAM consists of a CAS Latency of 4,and if the ddr2 SDRAM memory controller generated using MIG has a latency of 3? Does the design work together? Any help would be appreciated. Thanks. In present, ddr2 CAS Latency is defined for a
Hi all, I am interfacing ddr2 SDRAM controller in FPGA and I don't understand how can to read and write data to memory device using Microblaze processor and ddr2 SDRAM controller?. I'm studying about this controller and I don't know the operation of DQS signal in transferring data and the (...)
and by the way this s my first project If this is your first fpga project ever, and you are new to vhdl as well ... I would suggest that as a first project you try something simpler than anything to do with a ddr2 controller. Or expect a lot of pain^H^H^H^H opportunities to learn new and exciting things!
Hi all I am using MIG as a ddr2 controller for viretx5. I know that the FPGA's RAM's function has some problems in some memory addresss. I'm oing to detect those addresses. I'v generated the design . But after using chipscope, I found the error signal aways being asserted and there are no valid data on the rd_data_fifo_out (rd_data_valid (...)
hi, i'm learning ddr3 spec and would like to design a ddr3 memory controller. could anyone provide me some help about my question? 1. is the ZQ calibration function must supported in memory controller? ZQ calibration is used to calibration Ron and Rtt, is there any condition that the Ron&Rtt not need to calibration (...)
Before to use mig you need to choose witch memory do you want to use. For example ddr2 by micron and look at the data sheet about DQ an DQS. Dq is the data and DQs is strobe associed to this Data. more info at: XAPP858 - High-Performance ddr2 SDRAM Interface Data Capt
1. Interface the memory using a controller. It depends on: memory type (SRAM, SDRAM, DDR, ddr2, etc), then there are several posibilities: a) Write Your own memory controller. b) Use the available ipcore (opencore or bought one) c) Use special tool made by Your FPGA vendor. E.g. Xilinx (...)
Hi i think you can refer a chip name called dm365 ddr2/mddr guide, in google you find more info on it.. Venkat.k
Hi, Im using the XUPV5 Virtex-5 Board with Xilinx ISE 12.1. Within XPS I built up a system design where I instantiated a ddr2 SDRAM memory controller as a user IP-Core, which I created with MIG / core generator before. I connected all relevant ports with my user design and made all neccessary ports external (I also modified the ucf). My (...)
Hi, Im using the Xilinx XUPV5-LX110t development board and Xilinx ISE 12.1. I succussfully instantiated the memory controller with MIG and core generator. Now I'm not sure about the clocking of the controller. It has a sys_clk input and a clk200 clock. The connection of the 200MHz clock is clear for me, but i dont know from where to take (...)
HI, I am quite new to EDK. I need to read block of data through UART and write the same into ddr2 and then read from ddr2 and write into a fifo. and then read the fifo and send the data out. I am getting confused with reading EDK related materials. I am not getting wat to do.What all to read. Can any one help please.What all to read. How to s
Xilinx (and I would assume altera) use a calibration algorithm for ddr2. IIRC, it is in some of the JEDEC documents. the basic idea is to assume you can send valid commands, as well as write to the RAM. at this point, you write something that puts a known pattern out for each bit. eg 01010011. At this point, the data is re-read as often as pos
hi all, i have a ddr2 controller that works on 4 burst mode. ddr2 dq width is 16. i must provide 2, 32 bit data to the controller before writing it to memory. As well as when reading from a memory location it gives out 2, 32 bit data out. my processor is a master AHB, has a 32 bit (...)
Hi, I need to implement a ddr2 memory controller for an existing board. Therefore I used the core generator (10.1.03), did the settings accordingly and finished the "Create Design" To modify the pinout I started "Update Design" and selected an ucf including the ddr2 pinout of my board. After this, I found only the pin (...)
I'm interfacing a FPGA memory controller point to point to a 512Mb ddr2 SDRAM. What type of termination is needed on the address/DQ/we/cas/etc signals? The chip can clock up to 400mhz (800mhz ddr)
SDR is a sub set of the DDR memory which is faster and more complicated, if a device supports DDR or ddr2, then you can be sure that it supports SDR SDRAM.
Hi, can someone who has used Xilinx's MIG ddr2 controller help? i am trying to generate and simulate the ddr2 controller with memory MT47H16M16 memory model generated by MIG 2.0 (Xilinx ISE 10.1 > SP3) If someone has a tutorial or ise example. thanks in advance
Hi, I am using Xilinx Virtex5 to build a ddr2 SODIMM memory controller. It is working well at 200MHz while having calibration problems at 300MHz. after carefully debugging and simulation, I think that Xilinx calibration algorithm didn't work well for big skews (about 900 ps between DQS and its associated DQs) at 300MHz. Anyone has (...)
Hi, Bros I want to do some SI simulations to the ddr2 memory with SO-DIMM slot. I do not know the target memory Stick information, I mean it end user would probably use any memory stick. And I do not have the SPICE, RLGC or S-parameters of the SO-DIMM connector. But I know the IBIS model of memory (...)
i think you need to be more specifiv about your project. what is the memory controller for (sram,sdram,ddr,ddr2) what is the processor. what are the clock rates. what are the busses. what kind of transfers you want to use. (singel, bursts, pages)
I am writing veerilog code for ddr2 SDRAM controller using the micron memory module and I want to implement it on Virtex-4 FPGA.......but I am a new comer to verilog and due to time constraints I am afraid that i won't be able to write the complete code(complete all can any one provide me a synthesizable code......the one i cud get