Search Engine

Dds Core

Add Question

Are you looking for?:
dds design , dds and pic , ad9834 dds , dds sine
22 Threads found on Dds Core
short version: Add 2048 (12-bit half-scale) to your dds output, and use THAT result instead of what you use now. long version: see previous posts about 2's complement. The IP core output is 2's complement, and you are mistakenly treating it as an unsigned. That's why you get the curious sinewave wraparound as seen on the scope display. Also,
I believe both another forum member and I responded to this post, but now that it has been moved it no longer has those responses and a search didn't come up with any other similar posts for cosine dds that matches the original post. What is the point of moving threads if it corrupts the integrity of subsequent responses?
Hello! I'm facing the problem of simulating an FFT core generator in vhdl. I have written a FSM and a test bench file to run the simulation of the Xilinx FFT core (Streaming) in ISE. I'm using a dds module (from the core generator also) that generates a sinusoid at the input of the fft. What I'm getting at the (...)
I want how to simulate a dds core generated(xilinx ise) in modelsim and check out the output waveform?
Hi, I am generating 25MHz Sine wave using dds core. Simulation is working perfectly but hardware is not working. I am implementing simple dds core. Can you please tell me what can be the possible reason?
I am implementing the dds core but it is giving output without taking any data. Can you please help me what could be the possible problem.
Absolutely use dds IP core.. It's pretty easy to run and get data. It has also run-time frequency change option.
I'm using xilinx dds core in a spartan3 fpga. I have already make a signal with a desired frequency. since I change the valuse of "A", "DATA" and "WE" inputs in my VHDL code the output frequency does not changes. how could I make the output frequency to sweep?
Take a look at the dds Compiler in the core generator in xilinx ise. That might be what you are looking for....
And you can always use a dds achieve the same thing . If you are using xilinx ise it has got some dds ip core here is a good code example
Hello; I want to ask a few questions about performance of FPGA cores at high clock frequency. I'm trying to operate my system at 500 MHz. I will use FFT core, dds core, FIR filter core of xilinx with my system. I can generate a system with the cores at 500 mhz succesfully on ISE 11.5; (...)
Hi) I have a signal with bandwidth about 150Mhz and central frequency 200 Mhz. I need to divide it into 5 separate parts. So I want to down convert them by different frequency reference signals. Is it possible using dds core from Xilinx core generator? Any ideas...thanks
I'm under the impression, that the dds IP documentations have good explanations of it's basic operation, it's at least the case for the Altera dds core. It's very easy anyway. Simply consider an accumulator of any length, e.g. 32 bit. The frequency value is added each clock cycle, the accumulator is representing the signal phase. An (...)
Hi friend!, You cannot use Onchip PLL(DCM) at such low range frequency....Maybe you can try dds core to generate such freqs....Correct me if I'm wrong
I started to write a long-winded answer, and then remembered this: This is a data sheet for Xilinx's dds core, but there's plenty of information here for you to design your own.
Are you using a Xilinx device? Which one? Try the "dds Compiler" or "Direct Digital Synthesizer" cores included with Xilinx ISE core Generator. Or build your own dds. Feed a frequency constant into an ordinary arithmetic accumulator. Connect the accumulator output to the address inputs of a sinewave lookup table ROM. (...)
Which dds are you referring to? A core perhaps? If you only need the sinewave for HDL simulation, it's easier to use the sin() function.
What format is your dds output? Which language are you using?
hai iam using fft IPcore to implement on FPGA. IP core FFt needs 2's compliment no's as input. for simulating i am connecting dds o/p to FFt Input which is also IPcore. since dds o/p is not 2's compliment iam not able to get the fft out put correctly. can any body tell me how can i solve this problem? (...)
you can get NCO/dds Ip core for implementing on FPGA in ISE . Added after 1 minutes: you can get NCO/dds Ip core for implementing on FPGA in ISE .