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45 Threads found on edaboard.com: Decimation Frequency
I want to implement Radix-2 Single-path Delay Feedback (SDF) decimation-In-frequency FFT with Pipelining in VHDL and I am trying to understand the below architecture as described in this MIT OpenCo
Need C source code for Radix-22 FFT decimation-in-frequency algorithm. Need MATLAB code for Radix-2 FFT decimation-in-frequency algorithm.
The question title involves a contradiction in terms, because a CIC decimator is a filter with finite impulse response as well. So more exactly you are asking about using different FIR characteristics than CIC as a decimation filter. The general answer is quite simple, if you want a different frequency characteristic than (sin(x)/x)^n, you won't
Hi, Is there any way to simulate the frequency response of digital filters using Cadence Virtuoso? (like AC or PAC analyses done for analog filters) Actually, I am trying to realize a delta-sigma ADC in Cadence, which consists of a (digital) decimation filter. Can anybody give any idea how to simulate the performanc
Hi, I'm a bit unclear about a decimation filter used in oversampling data converters. Say in a delta sigma ADC that has a sampling frequency of 64 MHz, input frequency of 1 MHZ, oversampling equal to (64MHz/(2*1) = 32), and a 1-bit internal ADC, the resolution is supposed to be 20 bits. So there would be 64 samples at the output of the (...)
I use a 256 samples/sec ADC to measure some time-series voltage signal. The ADC stores the data points (total of N points) and then once the measurement is done, it transfer them to the PC. We have a C++ program that do some DSP. Specifically, it do three stages of Kaiser-based FIR filtering followed by decimation (4,2,2). Then, a Hanning-based FFT
You give the explanation in the question title. The minimal FIR filter order is related to the fs/fc ratio. With this sampling frequency, you can't make even a poor FIR filter with less than e.g. 500 or 1000 taps. Possible solutions: - design a multirate filter with decimation before the final filter - design an IIR filter. It must have incre
You need to educate yourself about multi-rate filters, decimation, and such. If you are sampling at 1K-samples/second, and you output every tenth sample your output rate is 100 samples/sec. If you output every hundredth sample, your data rate is 10 samples/second. In either case your SAMPLE rate is 1K samples/sec.
Is there an easy or straightforward way to analyze a frequency response plot/filter profile of a digital filter and determine it's architecture (number of taps, FIR vs IIR, decimation rate, coefficients, etc) For example, what information do i have about the filter and it's implementation by looking these plots (these are two different filters)
Hello I know how to plot the PSD after the modulator. but I don't know how to plot it after decimation filter ? any advice, tutorials Regards. Ali
I see two ways to downgrade SNR with unsuitable designed decimation: - bit width too low (generating quantization noise) - alias frequency suppression too low (insuffcient filter order related to the application) With correct designed decimation, there's no significant SNR degradation
Hello Everyone I am designing a decimation Filter for Delta Sigma ADC, the input to ADC is 3 KHz 0.5V peak to peak (0.25V to -0.25V) Sine wave but the output of decimation Filter (3367 taps FIR Low Pass Filter) is 3 KHz sine wave but the amplitude in the range of 0.507 to -0.507. How I should convert this value to equivalent voltage ? Can someon
These links may be irrelevant but interesting MDFT design Time Domain interval vs frequency Domain interval vs Sampling decimation interval. Not sure which either..
Hi ALL in now days i design FIXED POINT FIR that wil be implemented on FPGA the filtering unit using cic decimation followed by 2 fir LPF. the input to the unit is 32 bits - 30 fractions and 2 for real number. the end of the unit in 57 bits and i take just the fractions -51 downto 22. when i analyze the FILTER frequency RESPONSE ( for t
The output of the D-F/F is the modulated output, right? Yes. The output of a (1-bit) sigma delta modulator is a binary sequence representing the input signal. It's usually processed in a multi stage decimation filter to get the final output signal. The term "frequency range of the integrator" doesn't seem to make sense. You'll no
I don't understand about a CIC DC gain problem. A CIC decimator with power of two decimation factor is usually designed to have unity gain for the most significant bit and a bit width according to the application requirements. It doesn't make sense to refer gain to the output LSB, I think. frequency compensation with a FIR is reasonable however
i am trying to design a decimator for sigma delta converter for audio. my decimation factor is 128. from material i found i decided on a CIC filter for first stage (decimation of 64) and a half band FIR as second. so the CIC filter has 3 parameters - decimation factor , no of delay elements and the number of sections. i know the (...)
Hi techies, I am facing information loss in my spectrum after decimation. My 40MHz (with center frequency 40MHz) spectrum contains 8 sub-channel of QPSK having 5MHz bandwidth (respective center frequency of 22.5, 27.5, 32.5 ...52.5 and 57.5). Sampling freq of this spectrum is 160M. I am shifting this spectrum to baseband, so after (...)
Hi, I have a project called "pitch detection using LPC parameters with MATLAB code".The input voice is lowpass filtered a cut off frequency of about 900Hz and then the sampling rate (nominally 10kHz) is reduced to 2kHz by a decimation process.The decimated output is than analyzed using the autocorrelation method with a value of p=4 for the filter
I am designing a two stage filter to do decimation at the output of a Sigma Delta modulator. Here is the spec - Sampling frequency - Fs - 1.4MHz decimation factor - D - 100 Output resolution - 13 bits. The filter, and the modulator is reset every 100 clock cycles. To accomplish this, I used a 5 stage CIC filter to decimate by 20 (...)