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45 Threads found on edaboard.com: **Decimation Frequency**

I want to implement Radix-2 Single-path Delay Feedback (SDF) **decimation**-In-**frequency** FFT with Pipelining in VHDL and I am trying to understand the below architecture as described in this MIT OpenCo

Digital Signal Processing :: 04-21-2016 16:58 :: MjWasHere :: Replies: **0** :: Views: **829**

Need C source code for Radix-22 FFT **decimation**-in-**frequency** algorithm.
Need MATLAB code for Radix-2 FFT **decimation**-in-**frequency** algorithm.

Digital Signal Processing :: 06-12-2015 07:18 :: Hussein Mroueh :: Replies: **0** :: Views: **957**

The question title involves a contradiction in terms, because a CIC decimator is a filter with finite impulse response as well.
So more exactly you are asking about using different FIR characteristics than CIC as a **decimation** filter. The general answer is quite simple, if you want a different **frequency** characteristic than (sin(x)/x)^n, you won't

Digital Signal Processing :: 05-31-2015 08:50 :: FvM :: Replies: **1** :: Views: **978**

Hi,
Is there any way to simulate the **frequency** response of digital filters using Cadence Virtuoso? (like AC or PAC analyses done for analog filters)
Actually, I am trying to realize a delta-sigma ADC in Cadence, which consists of a (digital) **decimation** filter.
Can anybody give any idea how to simulate the performanc

ASIC Design Methodologies and Tools (Digital) :: 03-12-2015 14:11 :: jdp721 :: Replies: **0** :: Views: **873**

Hi,
I'm a bit unclear about a **decimation** filter used in oversampling data converters. Say in a delta sigma ADC that has a sampling **frequency** of 64 MHz, input **frequency** of 1 MHZ, oversampling equal to (64MHz/(2*1) = 32), and a 1-bit internal ADC, the resolution is supposed to be 20 bits. So there would be 64 samples at the output of the (...)

Analog Circuit Design :: 10-21-2014 15:28 :: mordak :: Replies: **0** :: Views: **583**

I use a 256 samples/sec ADC to measure some time-series voltage signal. The ADC stores the data points (total of N points) and then once the measurement is done, it transfer them to the PC. We have a C++ program that do some DSP. Specifically, it do three stages of Kaiser-based FIR filtering followed by **decimation** (4,2,2). Then, a Hanning-based FFT

Digital Signal Processing :: 06-26-2014 22:51 :: ali8 :: Replies: **0** :: Views: **610**

You give the explanation in the question title. The minimal FIR filter order is related to the fs/fc ratio. With this sampling **frequency**, you can't make even a poor FIR filter with less than e.g. 500 or 1000 taps.
Possible solutions:
- design a multirate filter with **decimation** before the final filter
- design an IIR filter. It must have incre

Digital Signal Processing :: 05-18-2014 22:10 :: FvM :: Replies: **2** :: Views: **662**

You need to educate yourself about multi-rate filters, **decimation**, and such. If you are sampling at 1K-samples/second, and you output every tenth sample your output rate is 100 samples/sec. If you output every hundredth sample, your data rate is 10 samples/second. In either case your SAMPLE rate is 1K samples/sec.

Microcontrollers :: 03-06-2014 13:12 :: barry :: Replies: **13** :: Views: **1632**

Is there an easy or straightforward way to analyze a **frequency** response plot/filter profile of a digital filter and determine it's architecture (number of taps, FIR vs IIR, **decimation** rate, coefficients, etc)
For example, what information do i have about the filter and it's implementation by looking these plots (these are two different filters)

Digital Signal Processing :: 01-09-2014 18:25 :: casey480 :: Replies: **0** :: Views: **463**

my ADC was 1 bit modulator
so I am confused for multibits data (after **decimation**)Do you understand **decimation** filter ?
Most simple **decimation** filter is cic filter. **frequency** characteristic of cic filter is same as moving averaging filter.
Output d

Digital Signal Processing :: 08-05-2013 17:19 :: pancho_hideboo :: Replies: **3** :: Views: **864**

I see two ways to downgrade SNR with unsuitable designed **decimation**:
- bit width too low (generating quantization noise)
- alias **frequency** suppression too low (insuffcient filter order related to the application)
With correct designed **decimation**, there's no significant SNR degradation

Digital Signal Processing :: 04-09-2013 17:46 :: FvM :: Replies: **1** :: Views: **1763**

Hello Everyone
I am designing a **decimation** Filter for Delta Sigma ADC, the input to ADC is 3 KHz 0.5V peak to peak (0.25V to -0.25V) Sine wave but the output of **decimation** Filter (3367 taps FIR Low Pass Filter) is 3 KHz sine wave but the amplitude in the range of 0.507 to -0.507. How I should convert this value to equivalent voltage ? Can someon

Digital Signal Processing :: 04-03-2013 11:45 :: Eminent.Engineer :: Replies: **4** :: Views: **879**

These links may be irrelevant but interesting
MDFT design
Time Domain interval vs **frequency** Domain interval vs Sampling **decimation** interval. Not sure which either..

Digital Signal Processing :: 05-31-2012 18:34 :: SunnySkyguy :: Replies: **4** :: Views: **872**

Hi ALL
in now days i design FIXED POINT FIR that wil be implemented on FPGA
the filtering unit using cic **decimation** followed by 2 fir LPF.
the input to the unit is 32 bits - 30 fractions and 2 for real number.
the end of the unit in 57 bits and i take just the fractions -51 downto 22.
when i analyze the FILTER **frequency** RESPONSE ( for t

Digital Signal Processing :: 05-06-2012 07:26 :: itmr :: Replies: **0** :: Views: **707**

The output of the D-F/F is the modulated output, right?
Yes. The output of a (1-bit) sigma delta modulator is a binary sequence representing the input signal. It's usually processed in a multi stage **decimation** filter to get the final output signal.
The term "**frequency** range of the integrator" doesn't seem to make sense. You'll no

Analog Circuit Design :: 04-06-2012 20:09 :: FvM :: Replies: **5** :: Views: **873**

I don't understand about a CIC DC gain problem. A CIC decimator with power of two **decimation** factor is usually designed to have unity gain for the most significant bit and a bit width according to the application requirements. It doesn't make sense to refer gain to the output LSB, I think.
**frequency** compensation with a FIR is reasonable however

Digital Signal Processing :: 11-26-2011 19:31 :: FvM :: Replies: **1** :: Views: **1242**

i am trying to design a decimator for sigma delta converter for audio. my **decimation** factor is 128. from material i found i decided on a CIC filter for first stage (**decimation** of 64) and a half band FIR as second.
so the CIC filter has 3 parameters - **decimation** factor , no of delay elements and the number of sections. i know the (...)

Digital Signal Processing :: 02-11-2011 20:42 :: steadymind :: Replies: **6** :: Views: **1933**

Hi techies,
I am facing information loss in my spectrum after **decimation**.
My 40MHz (with center **frequency** 40MHz) spectrum contains 8 sub-channel of QPSK having 5MHz bandwidth (respective center **frequency** of 22.5, 27.5, 32.5 ...52.5 and 57.5). Sampling freq of this spectrum is 160M.
I am shifting this spectrum to baseband, so after (...)

Digital Signal Processing :: 01-22-2011 14:48 :: bluespec9 :: Replies: **1** :: Views: **737**

Hi,
I have a project called "pitch detection using LPC parameters with MATLAB code".The input voice is lowpass filtered a cut off **frequency** of about 900Hz and then the sampling rate (nominally 10kHz) is reduced to 2kHz by a **decimation** process.The decimated output is than analyzed using the autocorrelation method with a value of p=4 for the filter

Digital Signal Processing :: 12-24-2010 22:01 :: magnitudee :: Replies: **0** :: Views: **3623**

I am designing a two stage filter to do **decimation** at the output of a Sigma Delta modulator. Here is the spec -
Sampling **frequency** - Fs - 1.4MHz
**decimation** factor - D - 100
Output resolution - 13 bits.
The filter, and the modulator is reset every 100 clock cycles.
To accomplish this, I used a 5 stage CIC filter to decimate by 20 (...)

ASIC Design Methodologies and Tools (Digital) :: 06-24-2010 18:40 :: analog_fever :: Replies: **0** :: Views: **761**

Hi,
Currently I am working on 2nd order sigma-delta ADC consist of 3rd order sinc filter.
I would like to know how much SNR degradation may occur because of the **decimation** filter ( due to noise folding & non-ideal response of sinc filter). Especially in the case when over-sampling ratio is very high (OSR > 256).
Please let me know how

Analog Circuit Design :: 05-25-2010 17:35 :: gen0357 :: Replies: **2** :: Views: **1802**

i need to implement a sigma delta ADC with 12 bit resolution at the output.
The sigma delta design has the modulator part followed by the digital **decimation** filter.
i have constructed the modulator part in "system vision"
now i require the DIGITAL **decimation** FILTER part in vhdl to complete the design.
Can somebody help me in how to construct th

PLD, SPLD, GAL, CPLD, FPGA Design :: 01-28-2010 14:58 :: rakesh045 :: Replies: **3** :: Views: **3375**

hello ,
i am a student in the high school of telecommunication of tunis and we are supposed to abord a the csd **decimation** as a project so the first task we are needed to do is to design a HB filter with fdatool .
the standard that we are working for is UMTS and the **frequency** is 200mhz ,so after passing by the sinus cardinal filter the (...)

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 11-15-2009 18:31 :: khalil.ajmi :: Replies: **0** :: Views: **968**

hello ,
i am a student in the high school of telecommunication of tunis and we are supposed to abord a the csd **decimation** as a project so the first task we are needed to do is to design a HB filter with fdatool .
the standard that we are working for is UMTS and the **frequency** is 200mhz ,so after passing by the sinus cardinal filter the (...)

Embedded Linux and Real-Time Operating Systems (RTOS) :: 11-15-2009 18:28 :: khalil.ajmi :: Replies: **0** :: Views: **951**

my Rf signal is 102.3 Mhz and it is fed to mixer and I need IF as 5Mhz so i set the local ocillator to 97.3Mhz to obtain the 5Mhz that is my IF.
I have to pass this IF through low pass filter and then **decimation** and obtain the same IF **frequency** as 5Mhz.
But my sampling **frequency** is 409.8Mhz for filter so i have to reduce to 20.49Mhz. (...)

Digital Signal Processing :: 06-22-2009 11:59 :: guest_1044 :: Replies: **1** :: Views: **1245**

My IF is 5Mhz.
I need to reduce my sampling **frequency** 409.8Mhz to 20.48 Mhz by using FIR lowpass filter, so i am decimating it in 2 stages , first time i am using cic filter and **decimation** factor 5 then i will get the new sampling **frequency** 81.9 which is given to half band filter by decimating factor 4 then we will obtain finally (...)

Digital Signal Processing :: 06-21-2009 09:33 :: guest_1044 :: Replies: **0** :: Views: **2098**

Hi,
i need to design the CIC **decimation** filter in VHDl for GSM **frequency**, i don't know nothing about CIC filter , if any one have detailed document for CIC filter design ,plz send it to my mail -id
Regards
kanimozhi.M

Digital Signal Processing :: 10-22-2008 07:52 :: Mkanimozhi :: Replies: **5** :: Views: **5387**

how to write the matlab code for **decimation** filter...consisting of one comb filter followed by two fir filter....how to start ...and which points to b considered for the design...

Digital Signal Processing :: 05-04-2008 03:12 :: triump.ar :: Replies: **1** :: Views: **2432**

Hi,
That's true - the question is: where is your sampling **frequency**, before **decimation**? (compared with highest **frequency** in your input signal)
If it's far enough (like 4x greater), you may simply drop every second sample. If not, say it, we'll talk about what to do then :).

Digital Signal Processing :: 02-19-2008 17:41 :: cheggy :: Replies: **4** :: Views: **3455**

Hi,
the **decimation** factor refers to input signal **frequency**, so if you have 100 ksample/s BEFORE **decimation** you'll have 1 ksample/s AFTER **decimation** (if you consider a factor equal to 100).
This happens because the **decimation** circuit select only one sample every 100 samples of the input signal.
In fact, (...)

Digital Signal Processing :: 11-19-2007 14:58 :: GertDalPozzo :: Replies: **1** :: Views: **784**

I know that the advantage of sigma delta ADC is the oversampling which reduce the requirements for the antialiasing filter, and moves the sampling noise to higher frequencies. As I read, the decimating filter attenuates the signals higher than Fs/2.
I use an sigma delta ADC (in PC soundcard), with the final sampling **frequency** of 8kHz. The useful

Analog Circuit Design :: 04-24-2007 19:44 :: Eugen_E :: Replies: **3** :: Views: **1148**

Need C source code for Radix-2 FFT **decimation**-in-**frequency** algorithm
Maybe this code will be useful for you
#include
#include
#include
#include
#define PI 3.14159265359
#define MAXPOW 24
struct complex
{
double r;
double i;
};
int pow_2

Digital Signal Processing :: 12-07-2006 08:27 :: Jools :: Replies: **14** :: Views: **19774**

Dear frens,
I am currently involve in asic design for designing a FFT radix-2 and radix-4 butterfly structure. I have done both design using verilog code. Eventually, i need to do some modification (improvement) on the design as a contribution to my postgraduate studies. Can anyone suggest to me any modification that can be done to the radix-4

PLD, SPLD, GAL, CPLD, FPGA Design :: 11-19-2006 09:00 :: siva_7517 :: Replies: **5** :: Views: **2951**

hi downsampling and **decimation** are same thing .
you can refer to understanding dsp by lyons for this.this concept is clearly given there.

Digital Signal Processing :: 07-17-2006 18:04 :: bm_soe :: Replies: **5** :: Views: **1646**

your answer is **decimation** and interpolation

Digital Signal Processing :: 07-13-2006 11:38 :: dsp_forall :: Replies: **3** :: Views: **846**

hi,
i want to implement a **decimation** filter on blackfin 533 processor which should decimate the input sequence by 4. i have read two technique to design such filter. According to the first technique, we wait four 4 samples to come to do the filtering process once. In this way we decimate the samples before filtering. The second approach can be to

Digital Signal Processing :: 02-22-2006 12:45 :: shameem :: Replies: **2** :: Views: **1365**

sir,
I want to implement 1024 point radix 4 **decimation** in **frequency** FFT on ACTEL FPGA.
I want the structure of radix 4 for 1024 point.
Please send the structure.
thank you
siva

Digital Signal Processing :: 01-05-2006 10:03 :: cisivakumar :: Replies: **1** :: Views: **1387**

Hi
Process gain is defined as improvement in signal to quantization ratio when using oversampling.
PG = 10 * log10(fs / (2 * BW))
BW = output BW after **decimation**.
To calculate PG you need to know BW, so specify the output BW or **decimation** ratio then i can help you.
Regards

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 12-13-2005 07:33 :: Circuit_seller :: Replies: **4** :: Views: **975**

Hi, I meet some problem in designing a **decimation** filter for a sigma-delta ADC
I don't have much experience in digital filter design, so I am quite confused when
look into the principle of the **decimation** filter.
Suppose we have a bit stream, the **frequency** is Fs and OSR is M
the averaging of M bits single can only produce an output of (...)

Analog Circuit Design :: 11-03-2005 06:35 :: yiyin :: Replies: **2** :: Views: **1410**

Hi,
I am trying to develop a function in Matlab to calculate FFT using DIF RADIX 2. In order to test it , firstly I am working with a signal with length =8 x= . Unfortunatelly it is not returning the correct result, I cant find what is wrong with the algorithm.
If somebody realise what is wrong in the code below, please let

Digital Signal Processing :: 10-22-2005 02:24 :: claudiocamera :: Replies: **1** :: Views: **9134**

explain the meaning of time **decimation** and **frequency** **decimation**.

Elementary Electronic Questions :: 06-17-2005 09:59 :: suvendu :: Replies: **2** :: Views: **4301**

hi,
polyphase **decimation** is an architecture that helps to reduce the clock **frequency** of operation by a factor M. for eg,if u do downsampling by 5 then u need to process only 2 samples out of 10 samples from the low pass filter it is sufficient to calculate just the 2 low pass filter samples in 10 cycles rather 10 sampls in 10 th

Digital Signal Processing :: 04-18-2005 17:45 :: viswa :: Replies: **3** :: Views: **1862**

Hi
I hope to answer to this question!
In Matlab Simulation for 4 stage CIC ( Cascade Integrator Comb filter ) filter ther are 4 stage Integratot and 4 stage Comb filter . these stage connect together by 1 sampling switch which decrease the sample **frequency** rate under **decimation** factor.
in my project sampling switch should switch every 2

Digital Signal Processing :: 03-14-2005 03:22 :: Rozita :: Replies: **0** :: Views: **1818**

How can I measure snr from sigma delta adc and **decimation** after that but not to predict the snr ?
In **frequency** domain low pass filter has perfect magnitude spectrum but I can't get the perfect mmse snr?I have already considered the delay on it.
If anyone has opoins plz tell me,thx.

Digital Signal Processing :: 12-26-2004 06:54 :: boeysue :: Replies: **7** :: Views: **3767**

A **decimation** filter uses a Cascaded-Integrator-Comb section
followed by a FIR section. The CIC section decimates down to 4
times the output sampling **frequency** and has a response of the
form (sin x over x)^n, n being higher than the order of the analog
section. The FIR can be any linear phase design, and is used for
antialias pourposes. If th

Analog Integrated Circuit (IC) Design, Layout and Fabrication :: 10-06-2004 21:54 :: tucura :: Replies: **3** :: Views: **2229**

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differential couple | lm35 with pic16f877a | hspice plot measure | hspice plot measure output | hall current sensor | project proteus com port | ads and component and symbol | 12v 19v | and loop and antenna | package and bonding