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Delay And Locked And Loop

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44 Threads found on edaboard.com: Delay And Locked And Loop
Consider a base delay of one or more cycles +/- a variable fraction.
The FFs in my simulation have a reset that need to be set to LOW. You should correct the schematic for clarity, but I see that you are actually using a Nand gate in simulation. There's apparently a problem with the reset timing of the DFF model, it seems to expect a longer signal duration. Adding some delay in the reset path sho
hi, I am doing a project on delay locked that i had a doubt that i tested the delay locked loop the output is like this.but in that result the ref clk and output of vcdl wont be locked exactly.can u suggest any idea where it went wrong . (...)
Hello everyone. I am studing DLL at the moment. Im trying to simulate my DLL Schematic and got curious about the 'locking time' The DLL's sub block 'Charge Pump' generates the 'Control Volatge' which is provided into the 'Voltage Controlled delay Line'. I was curious about the 'Control Voltage' locking time. Exactly when is (...)
Hi All, I have a very basic question, is the locking time of loop depends on the types Phase detector, means if i use PD using static logic (Nand gate) or PD using Dynamic logic(TSPC), which will have better smaller locking time and why(reason). please replay. Thanks
Hi, I am working on delay locked loop design. My concern is related to loop filter capacitor, does loop capacitor can cause loop stability issue. please help in this regards.
Hi, i am working on Voltage controlled delay line (VCDL) for delay locked loop(DLL). i started VCDL design using Replica Bias which is given in razavi book(Fig attached). as mentioned in book, For VDD= 3.3V , i kept VREF = 2.1V , so that to have swing of 1.2V. and kept both M3 (...)
Hi all, I was going through some docs on a mircrocontroller and I came across a couple of terms: Line locked Clock(LLC) and delay locked loop(DLL). I really do not the meaning of those. Can anyone plz explain me? Thanks in advance
Hi, Read about how DLL will fail to lock or falsely lock if the initial delay of the vcdl is not between 0.5T to 1.5T of the reference clock. How do i simulate this condition showing? How do i check if the locking is valid and not a false lock? Best Regards, de3n
Hi guys, Why do the locking time or cycle increases when the frequency increases? What is the reason or theory behind this. Thank you. :)
Hi, Am I using the correct way if testing the DLL? 1. Set 1 input pulse for clock reference at phase detector input. 2. Set 1 input pulse for clock in with a delay at VCDL input. Results: If the DLL is working properly, the clock reference from the phase detector input and clock out from the output of the VCDL would be able to align (...)
Hi, I need help with my DLL design which consist of a phase detector, charge pump loop filter and a voltage control delay line(VCDL). The input of the phase detector is fed by 2 clocks (clock reference and output clock with is a feedback from the output of the VCDL. The problem I am (...)
Hi guys, I'm doing a project on analog dll, any available references which I am able to refer to? such as design of the phase detector, charge pump and VCDL? please advice. :)
HI EVERYBODY AS I AM DOING A PROJECT IN "BIST CIRCUIT FOR DLL FAULT DETECTION",I WANT TO STUDY THE ANALOG delay locked loop CIRCUIT DESIGN and BIST circuit , C CAN ANYBODY SENDS THE REQURIED INFORMATION FOR THIS PROJECT.... THANKS..............
Thats what I was expecting, glad you stated it explicitly! Assuming you'll be targeting Xilinx devices. It has what you call delay locked loop(DLL), instead of PLL. To utilize DLL in your design you have to generate and instantiate HDL module in you design. Xilinx core generator will take parameter (...)
falsh locking happens when the delay line is too long or too short, where it goes 1 or more cycles ahead, and still can reach the lock status. don't know how to fix, might need very careful control at the beginning of locking operation, use a counter or something to limit your delayline range.
Hi all, I hope I could have some real help from the DLL experts in this forum. Let me first describe my problem referring to the attached file. Basically I want to make a delay locked loop. However, the delay lines inside the loop are composed of (1-delta%) (...)
Hello everyone, Has anybody tried simulating delay locked loop in simulink. I am starting off my thesis and it would be really helpful if anyone can attach the simulink files for DLL. I searched everywhere in this website and couldnt find any helpful information to start (...)
hi as far as i knew, in DDR-1 memory systems, only the memory controller has a DLL circuit (delay-locked-loop), but the memory chips dont have. so during writes the data and strobe have 90deg phase difference on the board traces, during reads, they have 0deg (controller makes the 90deg (...)
A DLL is a delay locked loop. Rather than adjust the phase until the error is zero, the output signal is delay with a tapped delay line and the taps are adjusted until the delay error is minimal. Zero error cannot usually be obtained because of the (...)