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72 Threads found on edaboard.com: Delay Locked
Hi, I'm using a chip which has a fault pin (open drain), it sets the fault pin (which is pulled to 3.3v) low if a problem happens. Now the problem is when I power up the circuit the pin is always set to low for a very short time until the chip is up and running. I have connected a Mosfet to that pin which on the other side pulls 3.3v to ground
Hi all, I designed delay locked lock which generate 8 phase output for USB2.0 chip (using pdk 65nm). However, I wonder how conditions noise of voltage supply (1V)? I added the sine signal on 1V supply but I don't know clearly magnitude and frequency of it??? and any more difference real conditions? My project will make real USB. So, it is very im
Consider a base delay of one or more cycles +/- a variable fraction.
Hello, sorry if this is a bit vague, but could anyone give me some tips on how to implement a TDC (based on tapped delay structure) in Simulink. There seems to be very little information online on how to simulate such a device in Simulink. I need it for simulation of an All-Digital Phase locked Loop.
The FFs in my simulation have a reset that need to be set to LOW. You should correct the schematic for clarity, but I see that you are actually using a NAND gate in simulation. There's apparently a problem with the reset timing of the DFF model, it seems to expect a longer signal duration. Adding some delay in the reset path sho
hi, I am doing a project on delay locked that i had a doubt that i tested the delay locked loop the output is like this.but in that result the ref clk and output of vcdl wont be locked exactly.can u suggest any idea where it went wrong . 102844. how to calculate the jitter and (...)
Hi everyone, For my master's thesis i need to do system level modeling of DLL in simulink to calculate jitter. Later on design has to be done in cadence. I could not find any reference to implement DLL in simulink. I am stuck with modeling of VCDL(voltage control delay line). Please guide me. thanks a lot!
Hello everyone. I am studing DLL at the moment. Im trying to simulate my DLL Schematic and got curious about the 'locking time' The DLL's sub block 'Charge Pump' generates the 'Control Volatge' which is provided into the 'Voltage Controlled delay Line'. I was curious about the 'Control Voltage' locking time. Exactly when is the loc
Hi All, I have a very basic question, is the locking time of loop depends on the types Phase detector, means if i use PD using static logic (NAND gate) or PD using Dynamic logic(TSPC), which will have better smaller locking time and why(reason). please replay. Thanks
Hi, I am working on delay locked loop design. My concern is related to loop filter capacitor, does loop capacitor can cause loop stability issue. please help in this regards.
Hi, i am working on Voltage controlled delay line (VCDL) for delay locked loop(DLL). i started VCDL design using Replica Bias which is given in razavi book(Fig attached). as mentioned in book, For VDD= 3.3V , i kept VREF = 2.1V , so that to have swing of 1.2V. And kept both M3 and M4 in linear region. The problem i am facing is : 1. The (...)
Hi all, I was going through some docs on a mircrocontroller and I came across a couple of terms: Line locked Clock(LLC) and delay locked Loop(DLL). I really do not the meaning of those. Can anyone plz explain me? Thanks in advance
Hi, Read about how DLL will fail to lock or falsely lock if the initial delay of the vcdl is not between 0.5T to 1.5T of the reference clock. How do i simulate this condition showing? How do i check if the locking is valid and not a false lock? Best Regards, de3n
Hi guys, Why do the locking time or cycle increases when the frequency increases? What is the reason or theory behind this. Thank you. :)
Yes, you can decrease the delay stage to achieve higher frequency operation. However, the lower limiter of frequency might be increased too. I am using 8 delay stages in and a bias circuit in the VCDL, what you mean is that I should reduce the number of delay stages in VCDL in order to reduce the delay of from the start of t
Hi, I need help with my DLL design which consist of a phase detector, charge pump loop filter and a voltage control delay line(VCDL). The input of the phase detector is fed by 2 clocks (clock reference and output clock with is a feedback from the output of the VCDL. The problem I am facing now is that I am unable to lock the reference clk and ou
A auto calibration circuit can be employed for 50% duty cycle correction. The principal is similar to the chargepump in PLL. The on time is used to charge while the off time is used to discharge. The output voltage of chargepump can be used for the edge delay controlling. This feedback loop will calibrate the duty cycle.
Hi guys, I'm doing a project on analog dll, any available references which I am able to refer to? such as design of the phase detector, charge pump and VCDL? please advice. :)
Good day... Please suggest any measures on how to effectively reduce jitter in a delay locked Loop. Thank you.
Good day everybody.. I am doing a delay locked loop.. I can't understand what went wrong... As shown in the figure below, the control voltage from the charge pump already settles (that's one of the criteria for locking ). But the output clock is still not locked with respect to the reference