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58 Threads found on edaboard.com: Derating
derating is due to capacitor ESR losses. Did you ever calculate the AC voltage across the capacitor? It should be below 10 V at 25 kHz. 30V @25 kHz for a 2.2 ?F capacitor means more than 10 A.
Well, depending on what you know about the grid, and your ability to limit / filter any upside excursions (like is it a small generator driven grid with occasional load-dump spikes, surges, ...) you might define your "380VAC" more conservatively, and this might make a derating exercise pick 1000V rather than 600V FETs. And like that. What you thin
The power is rated at a stated temperature. Read the fine print. Above stated temp the manufacturer provides this derating guidance. A part with a SOA "corner-cut" starting at 125C (case) with a 2C/W derating could be better for you (depending on real case temp that you can hold, by your thermal design) than a part rated at 70C with a -0.5C/W de
I'd go 2X the DC or pulse-peak worst case voltage for a fairly benign environment; more if you have abnormal conditions that expose it to worse. The derating regime (what's acceptable) varies a lot by application / end use and who's criticizing the design and components. In the snubber case realize that the worst case pulse stress may also be aff
Page 5 of this 5-way ERNI connector datasheet (as attached) says that it can carry 17 Amps (Total) at 100degC. However, the temperature derating graph (attached below) for this same connector suggests it can only carry 11.04 Amps over all 5 connector blades at 100degC?which is correct?....11.04 Amps, or 17 Amps?
Very good analysis albbg. Tantalum capacitors normally present low ESR, we can suggest appropriate based on voltage and ripple current rating and derating factors.
There's no specific aging mechanism that can be applied to calculate a lifetime. Running the capacitor with rated current 30K below the maximum full current temperature should give you sufficient margin. The current derating curve suggests that the current limits are calculated for 20K self heating which is quite a lot. There will some thermal s
if you have 80v rated fets that will see 80v in the circuit then that isn't really enough derating. You should pick higher voltage fets, eg100v, but see what the peak transient ring (if any) is across the fets when they switch.
The first of these attempts is the so-called basic OCV analysis. It relies on the fact that best- and worst-case conditions can?t occur at the same time. A single global derating factor is applied to delays to account for the fact that they will be somewhere between best and worst case in reality. This offers some improvement but becomes too cru
Hello, I have a question regarding OCV methodology. I work on a top level that contains a block (that I'm designing also) and I'm looking for the better methodology to apply OCV. At top-level the block is seen as a blak-box (LIB/LEF/GDSII) I use a flat OCV approach (different derating factors for setup/hold data/clock-launch/clock-capture
Hi, I would like to know if there is any difference between the K-factors seen in the liberty vs the derating factors we use for AOCVM ?? I have seen it written in many places as K-factor derating but since we have the K-factors in liberty and in case of multi-voltage it is 0 but we use AOCVM files i wanted to know the difference and why we c
Hi, I need calculate resistor 2.4 ohm let's say from Vishay: I am taking 100W power resistor with overload rating is x10 for 5s. Ambient temperature is 100deg. According graph derating it will be 80%. So effective power dissipation will be 80W. Now I need dissipate 3000W. The pulse duration the resistor withstand is 3000W/(80W*10(factor)*5s~1.
Power in MOSFET is I?R where R=0.85Ω The RdsOn spec for your part. The curve on page 5, using this indicates 2.2C/W derating of case temp with A vs Tc curve. This is close to my estimate of 1.5~2C/W. Get a better MOSFET. - - - Updated - - - In my opinion use the continuous ID.
Hysteretic regulators with 1% performance have been around for many years, but Zetex must have used their expertise in very low saturating switches and very fast recovery times to achieve these performance features. I like the thermistor regulation for 75'C derating the output drive. The nearby output Cap of 4.7uF is just there to smoothen the LE
Hi, Could somebody explain how derating values are calculated in OCV analysis and AOCV analysis? Thanks, Ravi Shankar.
from Synopsys: Advanced on-chip variation (AOCV) analysis reduces unnecessary pessimism by taking the design methodology and fabrication process variation into account. AOCV determines derating factors based on metrics of path logic depth and the physical distance traversed by a particular path. A longer path that has more gates tends to hav
Skin depth at 50 kHz is 0.3 mm for copper and even higher for bronze etc. contacts. Frequency dependent derating will be negligible. It's definitely a problem for thick conductor bars, e.g. high current connectors or contactors.
Referring to "ampacity" tables and it's derating according to number of circuits would be also my general answer. 1 mm wire diameter refers to about 0,75 mm?. As already mentioned, the standarized rating applies for standard conditions, so you possible arrive at different values for a specific applicat
You want to be very careful in looking at how that rating is specified; there are certain to be assumptions you must meet (case temp, use model (1A forever, 1A 10% of the time). You need to understand your environment - is there a credible fault scenario that could put you at (say) 2A for some period, and you need a 50% derating for confidence? S
Hi, you will need a library which is characterized for 1.0V with this library you can do your synthesis and your sdf simulations. Depending on your position regarding the foudary you may get this library or not. Or maybe your foundary does have a tool for derating an existing library. Maybe you already have some slow/worst case libraries which f